Features: · Low power consumption
· 20 MHz to 85 MHz shift clock support
·±1V common-mode range around 1.2V
· Narrow bus reduces cable size and cost
· High throughput (up to 2.38 Gbps throughput)
· Internal PLL with no external component
· Compatible with TIA/EIA-644 specification
·Devices are offered in 48- and 56-lead TSSOP packagesPinout
Specifications
| FIN3385MTDX |
Full Production |
RoHS Compliant |
$1.79 |
TSSOP |
56 |
TAPE REEL |
|
Line 1: $Y (Fairchild logo)
&Z (Asm. Plant Code)
&2 (2-Digit Date Code)
&K Line 2: FIN3385 |
* Fairchild 1,000 piece Budgetary Pricing
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| ** A sample button will appear if the part is available through Fairchild's on-line samples program. If there is no sample button, please contact a Fairchild distributor to obtain samples |
Package marking information for product FIN3385 is available. Click here for more information . |
Power Supply Voltage (VCC) -0.3V to +4.6V
TTL/CMOS Input/Output Voltage −0.5V to +4.6V
LVDS Input/Output Voltage -0.3V to +4.6V
LVDS Output Short Circuit Current (IOSD) Continuous
Storage Temperature Range (TSTG)−65°C to +150°C
Maximum Junction Temperature (TJ) 150°C
Lead Temperature (TL)
(Soldering, 4 seconds)260°C
ESD Rating (HBM, 1.5 kΩ, 100 pF)
I/O to GND >10.0 kV
All Pins>6.5 kV
ESD Rating (MM, 0Ω, 200 pF) >400V
Supply Voltage (VCC) 3.0V to 3.6V
Operating Temperature (TA)(Note 3) −10°C to +70°C
Maximum Supply Noise Voltage
(VCCNPP) 100 mVP-P (Note 4)
Note 3: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is eliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
Note 4: 100mV VCC noise should be tested for frequency at least up to 2 MHz. All the specification below should be met under such a noise.
DescriptionThe FIN3385 and FIN3383 transform 28-bit wide parallel LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low-Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock 28 bits of input LVTTL data are sampled and transmitted.
The FIN3386 and FIN3384 receive and convert the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the serializers and deserializers available. For the FIN3385, at a transmit clock frequency of 85MHz, 28-bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces.
FIN3385 Data Sheet
