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FIN1215

Features: • Low power consumption• 20 MHz to 85 MHz shift clock support• 50% duty cycle on the clock output of receiver• ±1V common-mode range around 1.2V• Narrow bus reduces cable size and cost• High throughput (up to 1.785 Gbps throughput)• Up to 595 Mbp...

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SeekIC No. : 004341629 Detail

FIN1215: Features: • Low power consumption• 20 MHz to 85 MHz shift clock support• 50% duty cycle on the clock output of receiver• ±1V common-mode range around 1.2V• Narrow bus r...

FIN1215 Data Sheet

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Part Number:
FIN1215
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/30

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Product Details

Description



Features:

• Low power consumption
• 20 MHz to 85 MHz shift clock support
• 50% duty cycle on the clock output of receiver
• ±1V common-mode range around 1.2V
• Narrow bus reduces cable size and cost
• High throughput (up to 1.785 Gbps throughput)
• Up to 595 Mbps per channel
• Internal PLL with no external component
• Compatible with TIA/EIA-644 specification
• Devices are offered in 48-lead TSSOP packages




Pinout

Connection Diagram




Specifications

Power Supply Voltage (VCC) ...............................-0.3V to +4.6V
TTL/CMOS Input/Output Voltage........................ −0.5V to +4.6V
LVDS Input/Output Voltage .................................-0.3V to +4.6V
LVDS Output Short Circuit Current (IOSD) ................Continuous
Storage Temperature Range (TSTG)............ −65°C to +150°C
Maximum Junction Temperature (TJ) ...............................150°C
Lead Temperature (TL)
(Soldering, 4 seconds) ....................................................260°C
ESD Rating (HBM, 1.5 kΩ, 100 pF)
LVDS I/O to GND ..........................................................>10.0 kV
All Pins (FIN1215, FIN1217 only) ....................................>6.5 kV
ESD Rating (MM, 0Ω, 200 pF)
(FIN1215, FIN1217 only) .................................................>400V



Product Product status Eco Status Pricing* Package type Leads Packing method Package Drawing Package Marking Convention**
FIN1215MTDX Full Production RoHS Compliant $2.67 TSSOP 48 TAPE REEL Line 1: $Y (Fairchild logo)
&Z (Asm. Plant Code)
&2 (2-Digit Date Code)
&K Line 2: FIN1215
* Fairchild 1,000 piece Budgetary Pricing
** A sample button will appear if the part is available through Fairchild's on-line samples program. If there is no sample button, please contact a Fairchild distributor to obtain samples

Package marking information for product FIN1215 is available. Click here for more information .





Description

The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low Voltage TTL) data into 3 serial LVDS (Low Voltage Differential Signaling) data streams. A phaselocked transmit clock of FIN1217 and FIN1215 is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock 21 bits of input LVTTL data are sampled and transmitted.

The FIN1218 and FIN1216 receive and convert the 3 serial LVDS data streams back into 21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the Serializers and Deserializers available. For the FIN1217, at a transmit clock frequency of 85 MHz, 21 bits of LVTTL data are transmitted at a rate of 595 Mbps per LVDS channel.

These chipsets of FIN1217 and FIN1215 are an ideal solution to solve EMI and cable size problems associated with wide and high-speed TTL interfaces.






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