FBL2033

Features:

• 8-bit transceivers
• Latched, registered or straight through in either A to B or B to A path
• Drives heavily loaded backplanes with equivalent load impedances down to 10W.
• High drive 100mA BTL Open Collector drivers on B-port
• Allows incident wave switching in heavily loaded backplane buses
• Reduced BTL voltage swing produces less noise and reduces power consumption
• Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Each BTL driver has a dedicated Bus GND for a signal return
• Controlled output ramp and multiple GND pins minimize ground bounce
• Glitch-free power up/power down operation
• Low ICC current
• Tight output skew
• Supports live insertion
• Pins for the optional JTAG boundary scan function are provided
• High density packaging in plastic Quad Flatpack
• 5V compatible I/O on A-port


Pinout




Specifications

SYMBOL	PARAMETER		RATING	UNIT
VCC	Supply voltage		-0.5 to +4.6	V
VIN	Input voltage	AI0 AI7, OEB0, OEBn, OEAn	-0.5 to +7.0	V
		B0 B7	-0.5 to +3.5
IIN	Input current	VIN< 0	-50
VOUT	Voltage applied to output in High output state		-0.5 to +7.0	V
LOUT	Current applied to output in Lowoutput state	AO0 AO7	64, 64	mA
		B0 B7	200
TSTG	Storage temperature		-65 to +150	°C

Description

The FBL2033 is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level side.

The FBL2033 common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A, SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a register, or a D-type latch.

When configured in the buffer mode, the FBL2033 inverse of the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-High latch enables. Regardless of the mode, data is inverted from input to output.

FBL2033 Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the Loopback input. When the Loopback input is High the output of the selected A-to-B logic element (not inverted) becomes the B-to-A input.

The FBL2033 3-State AO port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled. When either OEB0 is Low or OEB1 is High, the B-port is inactive and is pulled to the level of the pull-up voltage. New data can be entered in the flip-flop and latched modes or can be retained while the associated outputs are in 3-State (AO port) or inactive (B port).

The FBL2033 B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port ensure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V.

The B-port interfaces to "Backplane Transceiver Logic" (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes.

FBL2033 Output clamps are provided on the BTL outputs to further reduce switching noise. The "V_OH" clamp reduces inductive ringing effects during a Low-to-High transition. The "V_OH" clamp is always active. The other clamp, the "trapped reflection" clamp, clamps out ringing below the BTL 0.5V V_OL level. This clamp remains active for approximately 100ns after a High-to-Low transition.

To support live insertion, FBL2033 OEB0 is held Low during power on/off cycles to ensure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 3.3V level while V_CC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard
1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a V_CC pin.

The FBL2033 LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package.

Each FBL2033 BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble- shoot.