Features: • Full duplex, dual channel asynchronous receiver and transmitter• Quadruple-buffered receiver and transmitter• Stop bits programmable in 1/16-bit increments• Internal bit rate generator with 23 bit rates• Independent bit rate selection for each Rx and Tx...
Ei88C681: Features: • Full duplex, dual channel asynchronous receiver and transmitter• Quadruple-buffered receiver and transmitter• Stop bits programmable in 1/16-bit increments• Inter...
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The Epic Ei88C681/Ei68C681 DUART Dual Universal Asynchronous Receiver and Transmitter is a data communication device that provides two fully independent full duplex asynchronous communication channels in a single package. The DUART is designed for use in microprocessor based systems and may be used in a polled or interrupt driven environment.
Two basic versions of the DUART Ei88C681/Ei68C681 are available, each optimized for use with various microprocessor families: the 88C81 for 8085/85, 8080/88, Z80, Z8000, 68XX and 65XX family based systems., and the 68C681 for 68000 family based systems. A programmable mode of the Ei88C681 versions provides an interrupt daisy chain for use in Z80 and Z8000 based systems. The bus interfaces are however general enough to allow interfacing with other microprocessors and microcontrollers. The 88C681 and 68C681 are enhanced versions of the Signetics 2681 and the Motorola 68681, and are pin and function compatible with those devices. Each channel of the DUART may be independently programmed for operating mode and data format. The operating speed of each receiver and transmitter can beselected from baud rate generator, from the multi-purpose on chip counter/timer or from an external 1 x or 16 x clock.The bit rate generator can operate directly from a crystal connected across two pins or from an external clock. The ability to independently program the operating speed of the receiver and transmitter of each channel makes the DUART attractive for split-speed channel application such as clustered terminal systems. Both receive and transmit data is quadruple-buffered in on-chip FIFO to minimize the risk of receiver overrun or to reduce overhead in interrupt-driveapplications.