Ei68C153

The Ei68C153 Bus Interrupter Module (BIM) provides an interface between interrupting devices and a system bus such as the VMEbus or VERSAbus™. It generates a maximum of 7 bus interrupts on the IRQ1-IRQ7 outputs and responds to interrupt acknowledge cycles for up to 4 independent slaves.

The Ei68C153 BIM can also supply an interrupt vector during an interrupt acknowledge cycle. Moreover, it sits in the interrupt acknowledge daisychain which allows for multiple interrupts on the level acknowledged.

The Ei68C153 BIM accepts device interrupt requests on inputs INT0, INT1, INT2 and INT3. Each input is regulated by Bit 4 (IRE) of the associated control register (CRO controls INT0, CR! controls INT1,etc.). If IRE (Interrupt  Enable) is set and a device input is asserted, an Interrupt Request open-collector output (IRQ1 - IRQ7) is asserted. The asserted IRQX output is selected by the value programmed in Bits 0, 1, and 2 of the control register (L0, L1, and L3).

This Ei68C153 3-bit field determines the interrupt request level as set by software.

Two or more interrupt sources Ei68C153 can be programmed to the same request level. The corresponding IRQX output will remain asserted until multiple interrupt acknowledge cycles respond to all requests.

If the interrupt request level is set to zero, the interrupt is disabled because there is no corresponding IRQ output.