ETC5057

The ETC5057/ETC5054 family consists of A-law and law monolithicPCM CODEC/filtersutilizing theA/D and D/A conversionarchitectureshownin the block diagram below, and a serial PCM inter- face. The devices are fabricated using double- poly CMOS process. The encode portion of each device consists of an input gain adjust amplifier, an activeRC pre-filter which eliminates very high frequency noise prior to entering a switched-ca- pacitor band-passfilter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zerocircuitryand a compandingcoderwhich samples the filtered signal and encodes it in the companded A-law or law PCM format.

The de- code portion of each ETC5057/ETC5054 device consists of an ex- panding decoder, which reconstructs the analog signal from the compandedA-law or law code, a low-pass filter which corrects for the sin x/x re- sponse of the decoder output and rejects signals above 3400Hz and is followedby a single-ended power amplifiercapable of drivinglow impedance loads. The ETC5057/ETC5054 devices require 1.536 MHz, 1.544 MHz, or 2.048 MHz transmit and receive master clocks, which maybe asynchronous,transmit and receivebit clocks which may vary from 64 kHz to 2.048 MHz, and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industrystand- ard formats.