IC MAX II CPLD 1270 LE 144-TQFP
EPM1270GT144C5N: IC MAX II CPLD 1270 LE 144-TQFP
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Series: | MAX® II | Manufacturer: | Altera | ||
Programmable Type: | In System Programmable | Delay Time tpd(1) Max: | 6.2ns | ||
Available Set Gain : | 12 dB | Voltage Supply - Internal: | 1.71 V ~ 1.89 V | ||
Number of Logic Elements/Blocks: | 1270 | Number of Macrocells: | 980 | ||
Number of Gates: | - | Number of I /O: | 116 | ||
Operating Temperature: | 0°C ~ 85°C | Mounting Type: | Surface Mount | ||
Package / Case: | 144-LQFP | Supplier Device Package: | 144-TQFP (20x20) |
The EPM1270GT144C5N is designed as one member of the MAX II family of instant-on, non-volatile CPLDs. This family is based on a 0.18-m, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits.
EPM1270GT144C5N has many features. (1) Low-cost, low-power CPLD. (2) Instant-on, non-volatile architecture. (3) Standby current as low as 25A. (4) Provides fast propagation delay and clock-to-output times. (5) Provides four global clocks with two clocks available per logic array block (LAB). (6) UFM block up to 8 Kbits for non-volatile storage. (7) MultiVolt core enabling external supply voltages to the device of either 3.3V/2.5V or 1.8V. (8) MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels. (9) Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors. (10) Schmitt triggers enabling noise tolerant inputs (programmable per pin). (11) I/Os are fully compliant with the peripheral component interconnect special interest group (PCI SIG) PCI local bus specification, revision 2.2 for 3.3V operation at 66MHz. (12) Supports hot-socketing. (13) Built-in joint test action group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990. (14) ISP circuitry compliant with IEEE Std. 1532. That are all the main features.
Some specifications of EPM1270GT144C5N have been concluded into several points as follow. (1) Its LEs would be 1270. (2) Its typical equivalent macrocells would be 980. (3) Its equivalent macrocell range would be from 570 to 1270. (4) Its UFM size would be 8192bits. (5) Its maximum user I/O pins would be 212. (6) Its tPD1 would be 6.2ns. (7) Its fCNT would be 304MHz. (8) Its tSU would be 1.2ns. (9) Its tCO would be 4.6ns.
Also some absolute maximum ratings about EPM1270GT144C5N. (1) Its internal supply voltage would be min -0.5V and max 4.6V. (2) Its I/O supply voltage would be min -0.5V and max 4.6V. (3) Its DC input voltage would be min -0.5V and max 4.6V. (4) Its DC output current, per pin would be min -25mA and max 25mA. (5) Its storage temperature would be min -65°C and max 150°C. (6) Its ambient temperature would be min -65°C and max 135°C. (7) Its junction temperature would be max 135°C. And so on. If you have any question or suggestion or want to know more information please contact us for details. Thank you!
Technical/Catalog Information | EPM1270GT144C5N |
Vendor | Altera |
Category | Integrated Circuits (ICs) |
Programmable Type | In System Programmable |
Number of Macrocells | 980 |
Number of I /O | 116 |
Number of Logic Blocks/Elements | 1270 |
Operating Temperature | 0°C ~ 85°C |
Package / Case | 144-TQFP |
Features | - |
Voltage | 1.8V |
Memory Type | FLASH |
Delay Time tpd(1) Max | 6.2nS |
Packaging | Tray |
Lead Free Status | Lead Free |
RoHS Status | RoHS Compliant |
Other Names | EPM1270GT144C5N EPM1270GT144C5N 544 1387 ND 5441387ND 544-1387 |