EP324

Features: `High-performance EPLDs with 12 macrocells (EP312) or 24 macrocells (EP324) Combinatorial speeds as fast as 25 ns Counter frequencies of up to 33.3 MHz Pipelined data rates of up to 66 MHz`Multiple 20-pin PAL and GAL replacement and integration`Device erasure and reprogramming with advan...

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EP324 Picture
SeekIC No. : 004337036 Detail

EP324: Features: `High-performance EPLDs with 12 macrocells (EP312) or 24 macrocells (EP324) Combinatorial speeds as fast as 25 ns Counter frequencies of up to 33.3 MHz Pipelined data rates of up to 66 MHz...

floor Price/Ceiling Price

Part Number:
EP324
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

`High-performance EPLDs with 12 macrocells (EP312) or 24 macrocells (EP324)
Combinatorial speeds as fast as 25 ns
Counter frequencies of up to 33.3 MHz
Pipelined data rates of up to 66 MHz
`Multiple 20-pin PAL and GAL replacement and integration
`Device erasure and reprogramming with advanced, nonvolatile EPROM configuration elements
`Programmable registers providing D, T, JK, and SR flipflops with individual Clear and Clock controls
`Dual feedback on all macrocells for implementing buried registers with bidirectional I/O
`Programmable-AND /allocatable-OR structure allowing up to 16 product terms per macrocell
`Two product terms on all macrocell control signals
`Programmable inputs (8 in EP312, 10 in EP324) configurable as latches, registers, or flow-through input
`Available in windowed ceramic and one-time-programmable (OTP) plastic packages with 24 to 44 pins:
24-pin ceramic and plastic dual in-line package (CerDIP and PDIP)
28-pin plastic J-lead chip carrier (PLCC)
40-pin CerDIP and PDIP
44-pin PLCC
`One gl obal Clock pin; one global Input Latch Enable/Input Clock/Input (ILE /ICLK /INPUT ) pin
`Programmable "standby" option for low-power operation
`Programmable Security Bit for total protection of proprietary designs
`100% generically testable to provide 100% programming yield
`Software design support with the Altera PLDshell Plus software and a wide range of third-party tools; programming support through third-party vendors

 




Specifications

Symbol
Parameter
Conditions
Min
Max
Unit
VCC
Supply voltage
Note (2)
2.0
7.0
V
VI
DC input voltage
Notes (2), (3)
0.5
VCC + 0.5
V
TSTG
Storage temperature
65
150
° C
TAMB
Ambient temperature
Note (4)
10
85
° C



Description

The CMOS EPROM EP312 and EP324 devices have a versatile macrocell structure and I/O architecture, which allow them to implement highperformance logic functions effectively. The EP312 and EP324 input and macrocell features are a superset of features offered by PAL/GAL devices. Therefore, EP312 and EP324 devices can be used as an alternative to multiple PAL/GAL devices, SSI and MSI logic devices, or low-end gate arrays.




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