EP20K200BC356-1X

The EP20K200BC356-1X belonges to APEXTM 20K devices which are the first PLDs designed with the MultiCore architecture,conecting the strengths of LUT-based and productterm-based devices with an enhanced memory struc ture.LUT-based logic offers optimized performance and efficiency for data-path, registerintensive,mathematical,or digital signal processing (DSP) designs.

Features of the EP20K200BC356-1X are:(1)flexible clock management circuitry with up to four phase-locked loops: b uilt-in low-skew clock tree,up to eight global clock signals;(2)powerful I/O features:LVDS performance up to 840 Mb its per channel,individual tri-state output enable control for each pin,programmable output slew-rate control to redu ce switchingnoise;(3)advanced interconnect structure:available in a variety of packages with 144 to 1,020 pins, fine Line BGA packages maximize board space efficiency;(4)advanced software support:nativeLinkTM integration with po pular synthesis, simulation,and timing analysis tools;(5)industry's first programmable logic device (PLD)incorporatin g system-on-a-programmable-chip (SOPC) integration:ESB implementation of product-term logic used for combinator ial-intensive functions;(6)high density:up to 3,456 product-term-based macrocells.

The absolute maximum ratings of the EP20K200BC356-1X can be summarized as:(1):supply voltage(with respect to ground) is0.5V min and 3.6V max;(2):DC input voltage is2.0V min and 5.75V max;(3):DC output current per pin is25mA min and 25 mA max;(4):storage temperature(no bias) is65° C min and 150° C max; (5):ambient temp erature(under bias) is65°C min and 135°C max;(6):junction temperature(PQFP, RQFP, TQFP, and BGA package s,under bias) is 135°C max,junction temperature(ceramic PGA packages, under bias) is 150°C max.