EP1810LC-35T

The EP1810LC-35T is one member of the EP1810 family that offers a solution to high-speed, lowpower logic integration.It also supports 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates and contains on-board logic test circuitry to allow verification of function and AC specifications during standard production flow.

Features of the EP1810LC-35T are:(1)device erasure and reprogramming with non-volatile EPROM configuration elements;(2)complete device family with logic densities of 300 to 900 usable gates;(3)fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz;(4)programmable security bit for protection of proprietary designs;(5)100% generically tested to provide 100% mprogramming yield;(6)programmable registers providing D, T, JK, and SR flipflops with individual clear and clock controls;(7)programming support with Altera's Master Programming Unit (MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors.If you want to know more information such as the electrical characteristics about the EP1810LC-35T,please download the datasheet in www.seekic.com or www.chinaicmart.com .