EP1810LC-35

The EP1810LC-35 belongs to the EP1810 EPLD series. It offers LSI density, TTL-equivalent speed, and lowpower consumption. It is available in 68-pin plastic J-lead chip carrier (PLCC) package.

There are some features of EP1810LC-35 as follows. (1) high-performance,48-macrocell classic EPLD including counter frequencies of up to 50 MHz and pipelined data rates of up to 62.5 MHz; (2) programmable I/O architecture with up to 64 inputs or 48 outputs; (3) programmable clock option for independent clocking of all registers; (4) macrocells individually programmable as D,T,JK, or SR flipflops,or for combinatorial operation.

What comes next is some description on absolute maximum ratings of EP1810LC-35. (1): supply voltage (VCC) is from -2.0 V to 7.0 V; (2): DC input voltage (VI) is from -2.0 V to 7.0 V; (3): DC VCC or ground current (IMAX) is from -300 mA to 300 mA; (4): DC output current,per pin (IOUT) is from -25 mA to 25 mA; (5): storage temperature (Tstg) ranges from -65 to 150 ; (6): ambient temperature (Tamb) undre bias is from -65 to 135 ; (7): the maximum junction temperature (Tj) for ceramic package under bias is 150 and is 135 for plastic packages under bias. Then is about its DC characters. (1): high-level input voltage (VIH) is from 2.0 V to VCC+0.3 V; (2): low-level input voltage (VIL) is from -0.3 V to 0.8 V; (3): tri-state output leakage current (IOZ) is from -10 A to 10 A; (4): the maximum input pin capacitance (CIN) is 20 pF when VIN is 0 V and f is 1.0 MHz.