EP100

The EP100 PowerPC bus slave device is a bus interface unit designed for the PowerPC host bus. EP100 is designed to work on any 60x compliant bus architecture. EP100 has two user interfaces, one for interfacing with on-chip and off-chip user logic and register and the second interface is a direct interface to external asynchronous SRAM and synchronous BURST SRAM. The PowerPC slave works together with other devices or system controllers on the PowerPC bus. The slave can be assigned to a specific address space where it is mapped into. Access to the slave device is further directed to either the SRAM interface or the user interface bus based on address mapping.

The EP100 address mapping controller can be hardwired to the core or can be supplied by the user during run-time. The slave supports both the regular data transfer size and also the extended data transfer size specific to MPC8260. The slave handles address pipeline on the PowerPC bus with up to 2 outstanding requests.

While the slave is processing data transfer of one request, the EP100 CPU can start the address tenure of a second request. Address retry and separate address and data bus tenure are also supported by the slave. The slave detects data bus grant and data bus busy before starting its data tenure.