EM638165TS-6G

The EM638165TS-6G is one member of the EM638165 series.The EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

Features of the EM638165TS-6G are:(1)fast access time from clock: 5/6/6/6/7 ns; (2)fast clock rate: 166/143/133/125/100 MHz; (3)fully synchronous operation; (4)internal pipelined architecture; (5)1M word x 16-bit x 4-bank; (6)auto refresh and self refresh; (7)4096 refresh cycles/64ms; (8)CKE power down mode; (9)Single +3.3V ± 0.3V power supply; (10)interface:LVTTL; (11)54-pin 400 mil plastic TSOP II package.The EM638165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use.

The absolute maximum ratings of the EM638165TS-6G can be summarized as:(1)input, output voltage:-1.0 to 4.6V;(2)storage temperature:-55 to 125;(3)operating temperature:0 to 70;(4)soldering temperature (10 second):255;(5)power supply voltage:-1.0 to 4.6V;(6)power dissipation:1W;(7)short circuit output current:50mA.When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than  the refresh period (64ms) since the command does not perform any refresh operations.