EM48AM3284LBA

The EM48AM3284LBA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 4Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock.The 512Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS.

Features of the EM48AM3284LBA are:(1)Fully synchronous to positive clock edge; (2)LVCMOS Compatible with multiplexed address; (3)programmable burst length (B/L) - 1, 2, 4, 8 or full page; (4)programmable CAS latency (C/L) - 2 or 3; (5)data mask (DQM) for read / write masking; (6)burst read with single-bit write operation; (7)deep power down mode; (8)auto refresh and self refresh; (9)8,192 Refresh cycles / 64ms (7.8us).The normal drive strength got all outputs is specified to be LV-CMOS. By setting EMRS specific parameter on A6 and A5, driving capability of data output drivers is selected.

The absolute maximum ratings of the EM48AM3284LBA can be summarized as:(1)storage temperature range:-55 to 125;(2)operating temperature range:0 to 70;(3)input,output voltage range:-0.5 to 2.3V;(4)power supply voltage:-0.5 to 2.3V;(5)power dissipation:1W;(6)short circuit current:50mA.Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required, and these may be done before or after programming the Mode Register.