EM42AM3284LBC

The EM42AM3284LBC is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 4Meg words x 4 banks by 32 bits.The 512Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation.The data path internally prefetches multiple bits and EM42AM3284LBC transfers the datafor both rising and falling edges of the system clock.It means the doubled data bandwidth can be achieved at the I/O pins.

Features of the EM42AM3284LBC are:(1)internal double-date-rate architecture with 2 accesses per clock cycle; (2)1.8V ±0.1V VDD/VDDQ; (3)1.8V LV-COMS compatible I/O; (4)burst length (B/L) of 2, 4, 8, 16; (5)3 Clock read latency; (6)bi-directional,intermittent data strobe(DQS); (7)all inputs except data and DM are sampled at the positive edge of the system clock.; (8)data mask (DM) for write data; (9)sequential & interleaved burst type available; (10)auto precharge option for each burst accesses; (11)DQS edge-aligned with data for read cycles; (12)DQS center-aligned with data for write cycles; (13)No DLL ;CK to DQS is not synchronized; (14)deep power down mode; (15)partial array self-refresh(PASR); (16)auto temperature compensated self-refresh (TCSR) by built-in temperature sensor; (17)auto refresh and self refresh; (18)8,192 refresh cycles / 64ms.

The absolute maximum ratings of the EM42AM3284LBC can be summarized as:(1)storage temperature range:-55 to 125;(2)operating temperature range:0 to 70;(3)input,output voltage range:-0.5 to 2.3V;(4)power supply voltage:-0.5 to 2.3V;(5)power dissipation:1W;(6)short circuit current:50mA.Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality.