EDS2516CDTA

Features: • 2.5V power supply• Clock frequency: 133MHz (max.)• Single pulsed /RAS• ×16 organization• 4 banks can operate simultaneously and independently• Burst read/write operation and burst read/single write operation capability• 2 variations of burst se...

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EDS2516CDTA Picture
SeekIC No. : 004333897 Detail

EDS2516CDTA: Features: • 2.5V power supply• Clock frequency: 133MHz (max.)• Single pulsed /RAS• ×16 organization• 4 banks can operate simultaneously and independently• Burst r...

floor Price/Ceiling Price

Part Number:
EDS2516CDTA
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/31

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Product Details

Description



Features:

• 2.5V power supply
• Clock frequency: 133MHz (max.)
• Single pulsed /RAS
• ×16 organization
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• 2 variations of burst sequence
-Sequential (BL = 1, 2, 4, 8, full page)
-Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
-Auto refresh
-Self refresh
• TSOP (II) package with lead free solder (Sn-Bi)



Pinout

  Connection Diagram


Specifications

Parameter

Symbol

Rating

Unit

Voltage on any pin relative to VSS
VT
0.5 to VDD + 0.5 (3.6 (max.))
V
Supply voltage relative to VSS
VDD
0.5 to +3.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating temperature
TA
0 to +70
°C

Storage temperature

Tstg
55 to +125
°C

Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.




Description

The EDS2516CDTA is 256M bits SDRAMs organized as 4,194,304 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.

They are packaged in 54-pin plastic TSOP (II).




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