EDE2508ABSE-GE

• Power supply:  VDD, VDDQ = 1.85V ± 0.1V
• Double-data-rate architecture: two data transfers per clock cycle
• Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver
• DQS is edge aligned with data for READs: center-aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• Average refresh period  7.8µs at 0°C  TC +85°C 
                                          3.9s at +85°C < TC  +95°C
• SSTL_18 compatible I/O
• Posted CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
• Programmable RDQS, /RDQS output for making * 8 organization compatible to *4 organization
• /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation.
• FBGA (µBGA) package with lead free solder  (Sn-Ag-Cu) 
 

Parameter                                                Symbol                      Rating                       UNit               Notes

Power supply voltage                                 VDD                            1.0 to +2.3             V                      1

Power supply voltage for output                VDDQ                          0.5 to+ 2.3             V                      1

Power supply voltage for DLL                     VDDL                          0.5 to +2.3              V                      1

Input voltage                                              VIN                               0.5 to +2.3           V                      1

Output voltage                                           VOUT                        0.5 to +2.3                V                     1

Storage temperature                                  Tstg                            55 to +100                                 1,2
 
Power dissipation                                        PD                               1.0                         W                    1

Short circuit output current                        IOUT                              50                         mA                   1

The EDE2508ABSE is a 256M bits DDR2 SDRAM organized as 8,388,608 words × 8 bits × 4 banks.   It is packaged in 60-ball FBGA (µBGA^®) package. The EDE2516ABSE is a 256M bits DDR2 SDRAM organized as 4,194,304 words × 16 bits × 4 banks.   It is packaged in 84-ball FBGA (µBGA) package.