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EC603

Features: · High-performance, superscalar microprocessor- As many as three instructions issued and retired per clock- As many as Þve instructions in execution per clock- Single-cycle execution for most instructions· Four independent execution units and two register Þles- BPU featuring ...

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SeekIC No. : 004331387 Detail

EC603: Features: · High-performance, superscalar microprocessor- As many as three instructions issued and retired per clock- As many as Þve instructions in execution per clock- Single-cycle execution...

EC603 Data Sheet

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Part Number:
EC603
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

· High-performance, superscalar microprocessor
- As many as three instructions issued and retired per clock
- As many as Þve instructions in execution per clock
- Single-cycle execution for most instructions
· Four independent execution units and two register Þles
- BPU featuring static branch prediction
- A 32-bit IU
- LSU for data transfer between data cache and GPRs
- SRU that executes condition register (CR), special-purpose register (SPR) instructions, and integer add/compare instructions
- Thirty-two GPRs for integer operands
· High instruction and data throughput
- Zero-cycle branch capability (branch folding)
- Programmable static branch prediction on unresolved conditional branches
- Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
- A six-entry instruction queue that provides lookahead capability
- Independent pipelines with feed-forwarding that reduces data dependencies in hardware
- 16-Kbyte data cache-four-way set-associative, physically addressed; LRU replacement algorithm
- 16-Kbyte instruction cache-four-way set-associative, physically addressed; LRU replacement algorithm
- Cache write-back or write-through operation programmable on a per page or per block basis
- BPU that performs CR lookahead operations
- Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size
- A 64-entry, two-way set-associative ITLB
- A 64-entry, two-way set-associative DTLB
- Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
- Software table search operations and updates supported through fast trap mechanism
- 52-bit virtual address; 32-bit physical address
· Facilities for enhanced system performance
- A 32- or 64-bit split-transaction external data bus with burst transfers
- Support for one-level address pipelining and out-of-order bus transactions


Specifications

Characteristic Symbol Value Unit
Core supply voltage Vdd -0.3 to 2.75 V
PLL supply voltage AVdd -0.3 to 2.75 V
I/O supply voltage OVdd -0.3 to 3.6 V
Input voltage Vin
 -0.3 to 5.5 V
Storage temperature range Tstg
 -55 to 150

Notes
:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution : V in must not exceed OVdd by more than 2.5 V at any time, including during power-on reset.
3. Caution : OVdd must not exceed Vdd/AVdd by more than 1.2 V at any time, including during power-on reset.
4. Caution : Vdd/AVdd must not exceed OVdd by more than 0.4 V at any time, including during power-on reset.




Description

The following sections provide the package parameters and the mechanical dimensions for the PID7t. Note that the PID7t is currently offered only in the ceramic ball grid array (CBGA) package.




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