EBE52UD6ABSA

Features:

• 200-pin socket type small outline dual in line memory module (SO-DIMM) 
        -PCB height:  30.0mm 
        -Lead pitch:  0.6mm 
        -Lead-free
• 1.8V power supply
• Data rate: 533Mbps/400Mbps (max.)
• 1.8V (SSTL_18 compatible) I/O
• Double-data-rate architecture: two data transfers per clock cycle
• Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver
• DQS is edge aligned with data for READs: center-aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 
• Four internal banks for concurrent operation (Component)
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
• Posted CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe  operation.


Specifications

Parameter	Symbol	Value	Unit	Note
Voltage on any pin relative to VSS	VT	-0.5 to +2.3	V
Supply voltage relative to VSS	VDD	-0.5 to +2.3	V
Short circuit output current	IOS	50	mA
Power dissipation	PD	4	W
Operating ambient temperature	TC	0 to +85		1
Storage temperature	Tstg	-55 to +100

Description

The EBE52UD6ABSA is 64M words × 64 bits, 2 ranks DDR2 SDRAM Small Outline Dual In-line Memory Module,  mounting  8  pieces  of  512M  bits  DDR2 SDRAM sealed in FBGA (µBGA) package.  Read and write  operations  are  performed  at  the  cross  points  of the CK and the /CK.  This high-speed data transfer EBE52UD6ABSA is realized  by  the  4  bits  prefetch-pipelined  architecture.  Data  strobe  (DQS  and  /DQS)  both  for  read  and  write are  available  for  high  speed  and  reliable  data  bus design.  By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.  This  module EBE52UD6ABSA provides  high  density  mounting  without utilizing  surface  mount  technology.    Decoupling capacitors are mounted beside each FBGA (µBGA) on the module board.