EBE10RD4AEFA

Features:

• 240-pin socket type dual in line memory module (DIMM)
        -PCB height: 30.0mm
        -Lead pitch: 1.0mm
        -Lead-free
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate: 533Mbps/400Mbps (max.)
• SSTL_18 compatible I/O
• Double-data-rate architecture: two data transfers per clock cycle
• Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in capturing data at the receiver
• DQS is edge aligned with data for READs; center aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data referenced to both edges of DQS
• Four internal banks for concurrent operation (components)
• Burst length: 4, 8
• /CAS latency (CL): 3, 4, 5
• Auto precharge option for each burst access
• Auto refresh and self refresh modes
• Average refresh period
        -7.8µs at 0 TC +85
        -3.9µs at +85 < TC +95
• Posted CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe operation
• 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD)


Specifications

Parameter	Symbol	Value	Unit	Note
Voltage on any pin relative to VSS	VT	-0.5 to +2.3	V	1
Supply voltage relative to VSS	VDD	-0.5 to +2.3	V
Short circuit output current	IOS	50	mA	1
Power dissipation	PD	18	W
Operating ambient temperature	TC	0 to +95		1,2
Storage temperature	Tstg	-55 to +100		1

Description

The EBE10RD4AEFA is a 128M words × 72 bits, 1 rank DDR2 SDRAM Module, mounting 18 pieces of DDR2 SDRAM sealed in FBGA (µBGA®) package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer EBE10RD4AEFA is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (µBGA) on the module board.