EBD10RD4ADFA-E

Features:

• 184-pin socket type dual in line memory module (DIMM) 
        -PCB height:  30.48mm 
        -Lead pitch:  1.27mm 
        -Lead-free
• 2.5V power supply
• Data rate: 333Mbps/266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per clock cycle 
• Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver 
• Data inputs and outputs are synchronized with DQS 
• 4 internal banks for concurrent operation  (Components)
• DQS is edge aligned with data for READs; center aligned with data for WRITEs
•  Differential clock inputs (CK and /CK)
•  DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data referenced to both edges of DQS
• Auto precharge option for each burst access
• Programmable burst length:  2, 4, 8
• Programmable /CAS latency (CL):  2, 2.5
• Refresh cycles:  (8192 refresh cycles /64ms) 
        -7.8µs maximum average periodic refresh interval
• 2 variations of refresh 
        -Auto refresh 
        -Self refresh
• 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits) for Presence Detect (SPD) on PCB.


Specifications

Parameter	Symbol	Value	Unit	Note
Voltage on any pin relative to VSS	VT	-1.0 to +3.6	V
Supply voltage relative to VSS	VDD	-1.0 to +3.6	V
Short circuit output current	IOS	50	mA
Power dissipation	PD	18	W
Operating ambient temperature	TA	0 to +70		1
Storage temperature	Tstg	-55 to +125

Description

The EBD10RD4ADFA is 128M words × 72 bits, 1 ran Double  Data  Rate (DDR) SDRAM registered module mounting 18 pieces of 512M bits DDR SDRAM seale in TSOP package.  Read and  write operations ar performed at the cross points of the CK and the /CK This high-speed data transfer is realized by the  2-b prefetch-pipelined architecture.  Data strobe (DQS both for read and write are available for high speed an reliable data  bus design.  By setting extended mod register, the on-chip Delay Locked Loop (DLL) can bset enable or disable.  This EBD10RD4ADFA module provides hig density mounting  without utilizing surface moun technology.   Decoupling capacitors  are mounte beside each TSOP on the module board.