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E7500

Features: ` Processor/Host Bus Support-Intel® Xeon™ processor with 512-KB L2 cache-400 MHz system bus (2x address, 4x data)-Symmetric Multiprocessing Protocol (SMP) for up to two processors at 400 MT/s-System bus Dynamic Bus Inversion (DBI)-36-bit system bus addressing-12-deep in-order q...

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SeekIC No. : 004330696 Detail

E7500: Features: ` Processor/Host Bus Support-Intel® Xeon™ processor with 512-KB L2 cache-400 MHz system bus (2x address, 4x data)-Symmetric Multiprocessing Protocol (SMP) for up to two processor...

E7500 Data Sheet

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Part Number:
E7500
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

` Processor/Host Bus Support
-Intel® Xeon™ processor with 512-KB L2 cache
-400 MHz system bus (2x address, 4x data)
-Symmetric Multiprocessing Protocol (SMP) for up to two processors at 400 MT/s
-System bus Dynamic Bus Inversion (DBI)
-36-bit system bus addressing
-12-deep in-order queue
-AGTL+ bus driver technology with on-die termination resistors
-Parity protection on system bus data,address/request, and response signals
` Memory System
-One 144-bit wide DDR memory port (with Chipkill* technology ECC)
-Peak memory bandwidth of 3.2 GB/s
-Supports 64 Mb, 128 Mb, 256 Mb,512 Mb DRAM densities
-Supports a maximum of 16 GB of memory using (x4) double-sided DIMM
-Supports x72, Registered, ECC DDR DIMMs (in pairs)
` Hub Interface_A to Intel® ICH3-S
-Supports connection to ICH3-S via hub interface 1.5
-266 MB/s point-to-point hub interface 1.5 interface to ICH3-S
-Parity protected
-66 MHz base clock running 4x (533 MB/s) data transfer
-Isochronous support
-Parallel termination mode only
-64-bit addressing on inbound transactions (maximum 16 GB memory decode space)
` Hub Interface_B, Hub Interface_C, and Hub Interface_D
-Supports connection to Intel® P64H2 via HI 2.0
-Each hub interface is an independent 1 GB/s point-to-point 16-bit connection
-ECC protected
-66 MHz base clock running 8x (1 GB/s) data transfers
-Supports snooped and non-snooped inbound accesses
-Parallel termination mode
-64-bit inbound addressing
-32-bit outbound addressing supported for PCI-X
` PCI / PCI-X
-Supports 33 MHz PCI on ICH3-S
-Supports 33 MHz and 66 MHz PCI on P64H2
-Supports 66 MHz, 100 MHz or 133 MHz PCI-X on P64H2
` RASUM
-Supports S4EC/D4ED ECC
-Provides x4 Chipkill technology ECC support
-Correct any number of errors contained in a 4-bit nibble
-Detect all errors contained entirely within two 4-bit nibbles
-Hub Interface_A protected by parity
-Hub Interface_BD protected by ECC
-Memory auto-initialization by hardware implemented to allow main memory to be initialized with valid ECC
-Memory scrubbing supported
-SMBus target interface access to MCH error registers
-P64H2 and ICH3-S have SMBus target interface for access to registers
-ICH3-S master SMBus interface reads serial presence detect (SPD) on DIMMs
` Package
-1005-ball, 42.5 mm FC-BGA package


Specifications

Symbol
Parameter
Min
Max
Unit
Tstorage Storage Temperature
-55
150
°C
VCC_MCH 1.2 V Supply Voltage with respect to VSS
-0.38
2.1
V
VTT_AGTL Supply Voltage input with respect to VSS
-0.38
2.1
V
VDD_DDR DDR Buffer Supply Voltage
2
3
V



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