DSP96002

Features:

• Digital signal processing core
Efficient 32-bit DSP engine
Conforms to IEEE 754-1985 standard for single precision (32-bit) and single extended precision (44-bit) arithmetic
Up to 30 Million Instructions Per Second (MIPS) at 60 MHz
Parallel operation of Data ALU, Address Generation Unit (AGU), and program controller within the CPU allow more processing per instruction cycle
Single-cycle 32*32 bit parallel multiplier
Highly parallel instruction set with unique DSP addressing modes
Nested hardware DO loops
Instruction cache extended to operate as 4 K byte (1 K word)
Fast auto-return interrupts
Address buses:
• One 32-bit unidirectional internal X memory Address Bus (XAB)
• One 32-bit unidirectional internal Y memory Address Bus (YAB)
• One 32-bit internal Program Address Bus (PAB)
• Two 32-bit external address buses
Data buses:
• One 32-bit bidirectional internal X memory Data Bus (XDB)
• One 32-bit bidirectional internal Y memory Data Bus (YDB)
• One 32-bit bidirectional internal Global memory Data Bus (GDB)
• One 32-bit bidirectional internal DMA Data Bus (DDB)
• One 32-bit bidirectional internal Program Data Bus (PDB)
• Two 32-bit external data buses
MCU-like instruction set mnemonics make programming easier
• Memory
On-chip 1024*32-bit Program RAM
Two independent on-chip 512*32-bit data RAMs
Two independent on-chip 512*32-bit data ROMs (1024*32-bit virtual memory)
On-chip 64*32-bit bootstrap ROM
Off-chip expansion to 2*2*32*32-bit words of data memory
Off-chip expansion to 2*32*32-bit words of program memory
• Miscellaneous features
Two expansion ports assignable to X data, Y data, or program memory spaces or a combination thereof, effectively doubling off-chip bus bandwidth.
Host interface circuitry on each port provides a flexible slave interface to Direct Memory Access (DMA) controllers and external processors for easy design of multimaster systems
Write strobe pins support interface to external SRAMs without additional logic
Two programmable timers/counters
Three external interrupt/mode control lines
One external reset line for hardware reset
4-pin OnCE port for unobtrusive, processor speed-independent debugging
HCMOS design for operating frequencies from 60 MHz down to DC
223-pin plastic Pin Grid Array (PGA) package or 240-pin Ceramic Quad Flat Pack (CQFP) package
5.0 V power supply


Pinout




Specifications

Rating	Symbol	Value	Unit
Supply Voltage	Vcc	-0.3 to +7.0	V
All Input Voltages	Vin	GND 0.5 to VCC + 0.5	V
Current Drain per Pin excluding Vcc and VSS	I	10	mA
Operating Temperature Range	TJ	-40 to +105	°C
Storage Temperature	Tstg	-55 to +150	°C

Description

The DSP96002 is designed to support intensive graphic image and numeric processing. It is a dual-port, low-power, general purpose floating-point processor.

The DSP includes 1024 words of data RAM (equally divided into X data and Y data memory), 1024 words of fullspeed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA) controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCE™) debug circuitry.

The Central Processing Unit (CPU) consists of three 32-bit execution units operating in parallel. The DSP96002 has two identical memory expansion ports with control lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which facilitates easy interface with other processors for multiprocessor applications. Linear arrays of DSP96002s can be implemented without glue logic. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The high speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive applications that require floating-point processing and access to large memory subsystems.