DSP56857

Features:

• Efficient 16-bit hybrid controller engine with dual Harvard architecture
• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency
• Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC)
• Four (4) 36-bit accumulators, including extension bits
• 16-bit bidirectional shifter
• Parallel instruction set with unique addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Four hardware interrupt levels
• Five software interrupt levels
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/Enhanced OnCE debug programming interface




Application

• Multi-processor Telephony Systems
• Stand-alone MP3 player
• DTAD
• Feature phone
• Voice recognition and command
• Embedded modem/data pump
• LCD and keypad support
• General purpose devices
• Automotive hands-free




Description

Digital Signal Controller

The 56857 offers a rich feature set and on-chip memory in a 100-pin LQFP. It includes 80 KB of on-chip program SRAM and 48 KB of on-chip data SRAM. With two enhanced serial synchronous serial interfaces (ESSIs), this device can provide outputs for 5.1-channel surround sound.

The 56857 can be designed into multi-processor systems to provide internet audio and speech processing functionalities.