DSP56374

Features:

•150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25 V.
•Object Code Compatible with the 56K core.
•Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmatic support.
•Program Control with position independent code support.
•Six-channel DMA controller.
•Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4), Output divide factor (1, 2 or 4) and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise
•Internal address tracing support and OnCE for Hardware/Software debugging.
•JTAG port, supporting boundary scan, compliant to IEEE 1149.1.
•Very low-power CMOS design, fully static design with operating frequencies down to DC.
•STOP and WAIT low-power standby modes.
•6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM.
•6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM.
•20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism.
•6Kx24 Bit Program RAM.
•Various memory switches are available. See memory table below.


Pinout




Specifications

Rating1	Symbol	Value1, 2	Unit
Supply Voltage	VCORE_VDD, VPLLD_VDD	−0.3 to + 1.6	V
	VPLLP_VDD, VIO_VDD, VPLLA_VDD,	−0.3 to + 4.0	V
Maximum CORE_VDD power supply ramp time4	Tr	10	ms
All "5.0V tolerant" input voltages	VIN	GND − 0.3 to 5.5V	V
Current drain per pin excluding VDD and GND (Except for pads listed below)	I	12	mA
SCK_SCL	ISCK	16	mA
TDO	Ijtag	24	mA
Operating temperature range3	TJ	80 LQFP = 90 52 LQFP = 95	°C
Storage temperature	TSTG	−55 to +125
ESD protected voltage (Human Body Model)		1250	V
ESD protected voltage (Machine Model)	TSTG	75	V

Description

The DSP56374 is a high density CMOS device with 3.3 V inputs and outputs.

NOTE:This document contains information on a new product. Specifications and information herein are subject to change without notice.

Finalized specifications may be published after further characterization and device qualifications are completed.

The DSP56374 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale Semiconductor, Inc. (formerly Motorola) Symphony™ DSP family, as shown in Figure 1. Significant architectural enhancements include a barrel shifter, 24-bit addressing, and direct memory access (DMA). The DSP56374 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock.