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DSP56011

Application• Efficient, object-code compatible, 24-bit DSP56000 family DSP engine 47.5 Million Instructions Per Second (MIPS) with 21.05 ns instruction cycle at 95 MHz Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension byte Parall...

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SeekIC No. : 004329614 Detail

DSP56011: Application• Efficient, object-code compatible, 24-bit DSP56000 family DSP engine 47.5 Million Instructions Per Second (MIPS) with 21.05 ns instruction cycle at 95 MHz Highly parallel instru...

DSP56011 Data Sheet

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Part Number:
DSP56011
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Application

• Efficient, object-code compatible, 24-bit DSP56000 family DSP engine
   47.5 Million Instructions Per Second (MIPS) with 21.05 ns instruction cycle at 95 MHz
   Highly parallel instruction set with unique DSP addressing modes
   Two 56-bit accumulators including extension byte
   Parallel 24*24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
   Double precision 48*48-bit multiply with 96-bit result in 6 instruction cycles
   56-bit addition/subtraction in 1 instruction cycle
   Fractional and integer arithmetic with support for multi-precision arithmetic
   Hardware support for block-floating point Fast Fourier Transforms (FFT)
   Hardware nested DO loops
   Zero-overhead fast interrupts (2 instruction cycles)
   PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and power saving clock divider (2i : i = 0 to 15), which reduces clock noise
   Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories


Specifications

Rating1
Symbol
Value1, 2
Unit
Supply Voltage
VCC
-0.3 to +7.0
V
All input voltages
VIN
GND - 0.5 to VCC + 0.5
V
Current drain per pin excluding VCC and GND
I
10
mA
Operating temperature range
TJ
40 to +105
°C
Storage temperature
TSTG
-55 to +125
°C
.Notes:
1. GND = 0 V, VCC = 5.0 V ± 5%, TJ = 40°C to +105°C, CL = 50 pF + 2 TTL Loads
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device.


Description

The DSP56011 is a high-performance programmable Digital Signal Processor (DSP) developed for Digital Versatile Disc (DVD), High-Definition Television (HDTV), and Advanced Set-top audio decoding. The DSP56011 is optimized with audio-specific peripherals and customized memory configuration, and may be programmed with Motorola's certified software for Dolby AC-3 5.1 Channel Surround, Dolby Pro Logic, and MPEG1 Layer 2. These applications use Motorola s 24-bit DSP56000 architecture and are the highest quality solutions available. Flexible peripheral modules and interface software allow simple connection to a wide variety of video/ system decoders. In addition, the DSP56011 offers switchable memory space configuration, a large user-definable Program ROM and two independent data RAMs and ROMs, a Serial Audio Interface (SAI), Serial Host Interface (SHI), Parallel Host Interface (HI) with Direct Memory Access (DMA) for communicating with other processors, dedicated I/O lines, on-chip Phase Lock Loop (PLL), On-Chip Emulation (OnCE™) port, and on-chip Digital Audio Transmitter (DAX). Figure 1 shows the functional blocks of the DSP56011.




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