DS99R421

5 MHz43 MHz embedded clock & DC-Balanced data transmission (21 total LVDS data bits plus 3 low speed LVCMOS data bits)
User adjustable pre-emphasis driving ability through external resistor on LVDS outputs and capable to drive up to 10 meters shielded twisted-pair cable
Supports AC-coupling data transmission
100Ω Integrated termination resistor at LVDS input
Power-down control
Available @SPEED BIST to DS90UR124 to validate link integrity
All LVCMOS inputs & control pins have internal pulldown
Schmitt trigger inputs on OS[2:0] to minimize metastable conditions.
Outputs Tri-Stated through DEN
On-chip filters for PLLs
Power supply range 3.3V ± 10%
Automotive temperature range −40°C to +105°C
Greater than 8kV ESD Tolerance
Meets ISO 10605 ESD and AEC-Q100 compliance

The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and LVDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins.

The DS99R421 incorporates a single serialized LVDS signal on the high-speed I/O. Embedded clock LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the converter output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables.

DS99R421 Internal DC balanced encoding is used to support AC-Coupled interconnects.