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DS99R104

Features: ` 3 MHz40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions` Capable to drive shielded twisted-pair cable` User selectable clock edge for parallel data on both Transmitter and Receiver` Internal DC Balancing encode/decode Supports ACcoupling interface with no external...

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SeekIC No. : 004329479 Detail

DS99R104: Features: ` 3 MHz40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions` Capable to drive shielded twisted-pair cable` User selectable clock edge for parallel data on both Transmitt...

DS99R104 Data Sheet

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Part Number:
DS99R104
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` 3 MHz40 MHz clock embedded and DC-Balancing 24:1
  and 1:24 data transmissions
` Capable to drive shielded twisted-pair cable
` User selectable clock edge for parallel data on both
  Transmitter and Receiver
` Internal DC Balancing encode/decode Supports ACcoupling
  interface with no external coding required
` Individual power-down controls for both Transmitter and Receiver
` Embedded clock CDR (clock and data recovery) on
  Receiver and no external source of reference clock needed
` All codes RDL (random data lock) to support hot-pluggable applications
` LOCK output flag to ensure data integrity at Receiver side
` Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side
` PTO (progressive turn-on) LVCMOS outputs to reduce
  EMI and minimize SSO effects
` All LVCMOS inputs and control pins have internal pulldown
` On-chip filters for PLLs on Transmitter and Receiver
` Integrated 100 (±20%) termination in Receiver input
` 4 mA Receiver output drive
` 48-pin TQFP and 48-pin LLP packages
` Pure CMOS .35 m process
` Power supply range 3.3V ± 10%
` Temperature range −40°C to +85°C
` 8 kV HBM ESD structure


Specifications

Supply Voltage (VDD) ........................................−0.3V to +4V
LVCMOS/LVTTL Input Voltage ..............−0.3V to (VDD +0.3V)
LVCMOS/LVTTL Output Voltage ............−0.3V to (VDD +0.3V)
LVDS Receiver Input Voltage........................... −0.3V to 3.9V
LVDS Driver Output Voltage............................. −0.3V to 3.9V
LVDS Output Short Circuit Duration ..............................10 ms
Junction Temperature ................................................+150°C
Storage Temperature .................................−65°C to +150°C
Lead Temperature
(Soldering, 4 seconds) ...............................................+260°C
Maximum Package Power Dissipation Capacity Package
De-rating:
48L TQFP 1/JA °C/W above......................................... +25°C
DS99R103
JA ..............................................45.8 (4L*); 75.4 (2L*) °C/W
JC........................................................................... 21.0°C/W
DS99R104
JA............................................... 45.4 (4L*); 75.0 (2L*)°C/W
JC........................................................................... 21.1°C/W
48L LLP 1/JA °C/W above............................................ +25°C
DS99R103
JA ..................................................28 (4L*); 79.1 (2L*) °C/W
JC.............................................................................. 3.7°C/W
DS99R104
JA ....................................................28 (4L*); 79.1 (2L*)°C/W
JC............................................................................. 3.71°C/W
*JEDEC
ESD Rating (HBM)........................................................... ±8 kV


Description

The DS99R103/104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R103/104 incorporates LVDS signaling on the highspeed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the DS99R103/104 device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.




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