DS92LV1210

Features:

·Guaranteed transition every data transfer cycle
·Single differential pair eliminates multi-channel skew
·Flow-through pinout for easy PCB layout
·400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)
·10-bit parallel interface for 1 byte data plus 2 control bits
·Synchronization mode and LOCK indicator
·Programmable edge trigger on clock
·High impedance on receiver inputs when power is off
·Bus LVDS serial output rated for 27Ω load
·Small 28-lead SSOP package-MSA


Pinout




Specifications

Supply Voltage (V_CC)                                                                 −0.3V to +4V
CMOS/TTL Input Voltage                                               −0.3V to (V_CC +0.3V)
CMOS/TTL Output Voltage                                             −0.3V to (V_CC +0.3V)
Bus LVDS Receiver Input Voltage                                           −0.3V to +3.9V
Bus LVDS Driver Output Voltage                                             −0.3V to +3.9V
Bus LVDS Output Short
Circuit Duration Continuous
Junction Temperature                                                                       +150°C
Storage Temperature                                                       −65°C to +150°C
Lead Temperature (Soldering, 4 seconds)                                         +260°C
Maximum Package Power Dissipation Capacity @                                  25°C
Package:
28L SSOP                                                                                              1.27 W
Package Derating:
28L SSOP                                                             10.2 mW/°C above +25°C
ESD Rating (HBM)                                                                                     >5kV


Description

The DS92LV1021 transforms a 10-bit wide parallel CMOS/TTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1210 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and separates clock.

The DS92LV1021 may transmit data over heavily loaded backplanes or 10 meters of cable. The reduced cable, PCB trace count and connector size saves cost and makes PCB design layout easier. Clock-to-data and data-to-data skew are eliminated since one output will transmit both clock and all data bits serially. The powerdown pin is used to save power, by reducing supply current when either device is not in use. The Serializer has a synchronization mode that should be activated upon power-up of the device. The Deserializer will establish lock to this signal within 1024 cycles, and will flag Lock status. The embedded clock guarantees a transition on the bus every 12-bit cycle; eliminating transmission errors due to charged cable conditions. The DS92LV1021 output pins may be TRI-STATE ® to achieve a high impedance state. The PLL can lock to frequencies between 16 MHz and 40 MHz.