DS92LV1021A

Features:

·Guaranteed transition every data transfer cycle
·Single differential pair eliminates multi-channel skew
·Flow-through pinout for easy PCB layout
·400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)
·10-bit parallel interface for 1 byte data plus 2 control bits
·Programmable edge trigger on clock
·Bus LVDS serial output rated for 27Ω load
·Small 28-lead SSOP package-MSA


Pinout




Specifications

Supply Voltage                                                                   (V_CC) −0.3V to +4V
CMOS/TTL Input Voltage                                                  −0.3V to (V_CC +0.3V)
CMOS/TTL Output Voltage                                                −0.3V to (V_CC +0.3V)
Bus LVDS Receiver Input Voltage                                               −0.3V to +3.9V
Bus LVDS Driver Output Voltage                                                 −0.3V to +3.9V
Bus LVDS Output Short Circuit Duration Continuous
Junction Temperature                                                                          +150°C
Storage Temperature                                                          −65°C to +150°C
Lead Temperature (Soldering, 4 seconds)                                            +260°C
Maximum Package Power Dissipation Capacity@                                      25°C
Package:
28L SSOP                                                                                                 1.27 W
Package Derating:
28L SSOP                                                                10.2 mW/°C above +25°C
ESD Rating (HBM)                                                                                     >2.0kV
(Note 1)
Note 1: With a limited Engineering sample size,
ESD (HBM) testing passed                                                                          2.5kV


Description

The DS92LV1021A transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1021A can transmit data over backplanes or cable.

The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits both clock and data bits serially, it eliminates clockto-data and data-to-data skew. The powerdown pin saves power by reducing supply current when the device is not being used. Upon power up of the Serializer, you can choose to activate synchronization mode or use one of National Semiconductor's Deserializers in the synchronization-torandom-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the DS92LV1021A output pins into TRI-STATE® to achieve a high impedance state. The PLL can lock to frequencies between 16 MHz and 40 MHz.