DS92CK16

Features:

·Master/Slave clock selection in a backplane application
·125 MHz operation (typical)
·100 ps duty cycle distortion (typical)
·50 ps channel to channel skew (typical)
·3.3V power supply design
·Glitch-free power on at CLKI/O pins
·Low Power design (20 mA @ 3.3V static)
·Accepts small swing (300 mV typical) differential signal levels
·Industrial temperature operating range (-40°C to +85°C)
·Available in 24-pin TSSOP Packaging


Pinout




Specifications

Supply Voltage (V_CC)                                                             −0.3V to +4V
Enable Input Voltage (DE, OE, CrdCLKIN)                              −0.3V to +4V
Voltage (CLKOUT)                                                     −0.3V to (V_CC + 0.3V)
Voltage (CLKI/O±)                                                                 −0.3V to +4V
Driver Short Circuit Current momentary
Receiver Short Circuit Current momentary
Maximum Package Power Dissipation at                                        +25°C
TSSOP Package                                                                           1500 mW
Derate TSSOP Package                                    8.2 mW/°C above +25°C
JA                                                                                               95°C/W
JC                                                                                               30°C/W
Storage Temperature Range                                       −65°C to +150°C
Lead Temperature Range (Soldering, 4 sec.)                                 260°C
ESD Ratings: HBM (Note 2)                                                            >3000V
CDM (Note 2)                                                                                 >1000V
Machine Model (Note 2)                                                                   >200V


Description

The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low power dissipation, low noise, and high data rates. The BLVDS side is a transceiver with a separate channel acting as a return/source clock.

The DS92CK16 accepts BLVDS (300 mV typical) differential input levels, and translates them to 3V CMOS output levels.

An DS92CK16 output enable pin OE , when high, forces all CLKOUT pins high.

The DS92CK16 device can be used a source synchronous driver. The selection of the source driving is controlled by the CrdCLKIN and DE pins. This device can be the master clock, driving the inputs of other clock I/O pins in a multipoint environment.

Easy master/slave clock selection is achieved along a backplane.