DS90CR562

Features:

·Up to 105 Megabyte/sec bandwidth
·Narrow bus reduces cable size and cost
·290 mV swing LVDS devices for low EMI
·Low power CMOS design
·Power-down mode
·PLL requires no external components
·Low profile 48-lead TSSOP package
·Rising edge data strobe
·Compatible with TIA/EIA-644 LVDS standard


Pinout




Specifications

Supply Voltage (V_CC)                                                            −0.3V to +6V
CMOS/TTL Input Voltage                                         −0.3V to (V_CC + 0.3V)
CMOS/TTL Ouput Voltage                                        −0.3V to (V_CC + 0.3V)
LVDS Receiver Input Voltage                                   −0.3V to (V_CC + 0.3V)
LVDS Receiver Input Voltage                                   −0.3V to (V_CC + 0.3V)
LVDS Output Short Circuit Duration continuous
Junction Temperature                                                                  +150°C
Storage Temperature Range                                       −65°C to +150°C
Lead Temperature (Soldering, 4 sec.)                                          +260°C
Maximum Power Dissipation @                                                       +25°C
MTD48 (TSSOP) Package:
DS90CR561                                                                                      1.98W
DS90CR562                                                                                      1.89W
Package Derating:
DS90CR561                                                       16 mW/°C above +25°C
DS90CR562                                                       15 mW/°C above +25°C


Description

The DS90CR561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR562 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 105 Megabytes per second. These devices are offered with rising edge data strobes for convenient interface with a variety of graphics and LCD panel controllers.

This DS90CR562 chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.