DS90CR485

Features:

·Up to 6.384 Gbps throughput
·66MHz to 133MHz input clock support
·Reduces cable and connector size and cost
·Pre-emphasis reduces cable loading effects
·DC balance reduces ISI distortion
·24 bit double edge inputs
·3V Tolerant LVCMOS/LVTTL inputs
·Low power, 2.5V supply
·Flow-through pinout
·In 100-pin TQFP package
·Conforms with TIA/EIA-644-A LVDS standard.


Pinout




Specifications

Supply Voltage (V_CC)                                                        −0.2V to +2.7V
Supply Voltage (V_CC3)                                                      −0.3V to +3.6V
LVCMOS/LVTTL Input Voltage                               −0.3V to (V_CC3 + 0.3V)
LVDS Output Voltage                                              −0.3V to (V_CC + 0.3V)
LVDS Short Circuit Duration Continuous
Maximum Package Power Dissipation @                                         25°C
100 TQFP Package                                                                            2.9W
Derate TQFP Package                                    23.8mW/°C above +25°C
Lead Temperature (Soldering, 4 sec.)                                         +260°C
Junction Temperature                                                                  +150°C
Storage Temperature Range                                       −65°C to +150°C
ESD Rating: (HBM, 1.5kΩ, 100pF)
I/O and Control Pins                                                                        > 2 kV
All Supply and GND pins                                                                 > 1.5kV
(EIAJ, 0Ω, 200pF)                                                                            > 200V


Description

The DS90CR485 serializes the 24 LVCMOS/LVTTL double edge inputs (48 bits data latched in per clock cycle) onto 8 Low Voltage Differential Signaling (LVDS) streams. A phaselocked transmit clock is also in parallel with the data streams over a 9th LVDS link. The reduction of the wide TTL bus to a few LVDS lines reduces cable and connector size and cost.

The DS90CR485 double edge input strobes data on both the rising and falling edges of the clock. This minimizes the pin count required and simplifies PCB routing between the host chip and the serializer.

This chip is an ideal solution to solve EMI and interconnect size problems for high throughput point-to-point applications.

The DS90CR485 is intended for use with the DS90CR486Channel-Link receiver. It is also backward compatible with other Channel-Link receiver such as the DS90CR482 and DS90CR484.

For more details about DS90CR485, please refer to the "Applications Information" section of this datasheet.