DS90CF584

Features:

·20 to 65 MHz shift clk support
·Up to 227 Mbytes/s bandwidth
·Cable size is reduced to save cost
·290 mV swing LVDS devices for low EMI
·Low power CMOS design (< 550 mW typ)
·Power-down mode saves power (< 0.25 mW)
·PLL requires no external components
·Low profile 56-lead TSSOP package
·Falling edge data strobe
·Compatible with TIA/EIA-644 LVDS standard
·Single pixel per clock XGA (1024 x 768)
·Supports VGA, SVGA, XGA and higher
·1.8 Gbps throughput


Pinout




Specifications

Supply Voltage (V_CC)                                                                −0.3V to +6V
CMOS/TTL Input Voltage                                              −0.3V to (V_CC + 0.3V)
CMOS/TTL Output Voltage                                            −0.3V to (V_CC + 0.3V)
LVDS Receiver Input Voltage                                        −0.3V to (V_CC + 0.3V)
LVDS Driver Output Voltage                                          −0.3V to (V_CC + 0.3V)
LVDS Output Short Circuit Duration Continuous
Junction Temperature                                                                       +150°C
Storage Temperature                                                      −65°C to +150°C
Lead Temperature (Soldering, 4 sec)                                               +260°C
Maximum Power Dissipation @                                                             25°C
MTD56 (TSSOP) Package:
DS90CF583                                                                                         1.63W
DS90CF584                                                                                         1.61W
Package Derating:
DS90CF583                                                       12.5 mW/°C above +25°C
DS90CF584                                                       12.4 mW/°C above +25°C


Description

The DS90CF583 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF584 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CONTROL are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers.

This DS90CF583 chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.