DS90CF582

Features:

·Up to 140 Megabyte/sec Bandwidth
·Narrow bus reduces cable size
·345 mV swing LVDS devices for low EMI
·Low power CMOS design
·Power-down mode
·PLL requires no external components
·Low profile 56-lead TSSOP package
·Falling edge data strobe
·Compatible with TIA/EIA-644 LVDS standard


Pinout




Specifications

Supply Voltage (V_CC)                                                                    -0.3 to +6V
CMOS/TTL Input Voltage                                                 -0.3 to (V_CC + 0.3V)
CMOS/TTL Output Voltage                                               -0.3 to (V_CC + 0.3V)
LVDS Receiver Input Voltage                                           -0.3 to (V_CC + 0.3V)
LVDS Driver Output Voltage                                            -0.3 to (V_CC + 0.3V)
LVDS Output Short Circuit Duration continuous
Junction Temperature                                                                         +150
Storage Temperature Range                                                 -65 to +150
Lead Temperature (Soldering, 4 sec.)                                                 +260
Maximum Package Power Dissipation @                                               +25
MTD56 (TSSOP) Package: DS90CF581                                                 1.63W
DS90CF582                                                                                          1.61W
Derate Package: DS90CF581                                  12.5 mW/ above +25
DS90CF582 12.4 mW/ above +25


Description

The DS90CF581 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF582 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CNTL) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 140 Megabytes per second. The DS90CF581 chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.