DS90CF581

Features:

·Up to 140 Megabyte/sec Bandwidth
·Narrow bus reduces cable size and cost
·290 mV swing LVDS devices for low EMI
·Low power CMOS design
·Power-down mode
·PLL requires no external components
·Low profile 56-lead TSSOP package
·Falling edge data strobe
·Compatible with TIA/EIA-644 LVDS standard


Pinout




Specifications

Supply Voltage (V_CC)                                                          −0.3 to +6V
CMOS/TTL Input Voltage                                       −0.3 to (V_CC + 0.3V)
LVDS Driver Output Voltage                                  −0.3 to (V_CC + 0.3V)
LVDS Output Short Circuit Duration continuous
Junction Temperature                                                             +150°C
Storage Temperature Range                                  −65°C to +150°C
Lead Temperature (Soldering, 4 sec.)                                     +260°C
Maximum Package Power Dissipation @                                    +25°C
MTD56 (TSSOP) Package: DS90CF581                                         1.63W
Derate Package: DS90CF581                    12.5 mW/°C above +25°C


Description

The DS90CF581 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 40 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CNTL) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 140 Megabytes per second. This transmitter is intended to interface to any of the FPD Link receivers.

The chipset DS90CF581 is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.