DS90CF388A

SpecificationsFunctionReceiverColor Depth24 bppPixel Clock Max112 MHzPixel Clock Min32.5 MHzOutput CompatibilityLVCMOSTotal Throughput6272 MbpsPayload/Channel784 MbpsSupply Voltage3.3 VoltTemperature Min-10 deg CTemperature Max70 deg CDisplayTypeFPDSensing & ImagingYes View Using CatalogDescriptio...

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SeekIC No. : 004329342 Detail

DS90CF388A: SpecificationsFunctionReceiverColor Depth24 bppPixel Clock Max112 MHzPixel Clock Min32.5 MHzOutput CompatibilityLVCMOSTotal Throughput6272 MbpsPayload/Channel784 MbpsSupply Voltage3.3 VoltTemperatur...

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Part Number:
DS90CF388A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Specifications

FunctionReceiver
Color Depth24 bpp
Pixel Clock Max112 MHz
Pixel Clock Min32.5 MHz
Output CompatibilityLVCMOS
Total Throughput6272 Mbps
Payload/Channel784 Mbps
Supply Voltage3.3 Volt
Temperature Min-10 deg C
Temperature Max70 deg C
DisplayTypeFPD
Sensing & ImagingYes
View Using Catalog



Description

The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second).

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects.

The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers.

This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the "Applications Information" section of this datasheet.

Reliability Metrics


Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
DS90CF388AVJD .35 0 18700 0 0 1290000 3 366041022
DS90CF388AVJDX .35 0 18700 0 0 1290000 3 366041022

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


Design Tools


Title Size in Kbytes Date    
Evaluation Kit for +3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA     View    

If you have trouble printing or viewing PDF file(s), see Printing Problems.

More Application Notes


Title Size in Kbytes Date
AN-1127: Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link 25 Kbytes 4-Oct-04 Download
AN-1163: Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 13 Kbytes 15-May-04 Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.




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