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DS90CF386

Features: ·20 to 85 MHz shift clock support·Rx power consumption <142 mW (typ) @85MHz Grayscale·Rx Power-down mode <1.44 mW (max)·ESD rating >7 kV (HBM), >700V (EIAJ)·Supports VGA, SVGA, XGA and Single Pixel SXGA.·PLL requires no external components·Compatible with TIA/EIA-644 LVDS sta...

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SeekIC No. : 004329340 Detail

DS90CF386: Features: ·20 to 85 MHz shift clock support·Rx power consumption <142 mW (typ) @85MHz Grayscale·Rx Power-down mode <1.44 mW (max)·ESD rating >7 kV (HBM), >700V (EIAJ)·Supports VGA, SVGA,...

DS90CF386 Data Sheet

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Part Number:
DS90CF386
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

·20 to 85 MHz shift clock support
·Rx power consumption <142 mW (typ) @85MHz Grayscale
·Rx Power-down mode <1.44 mW (max)
·ESD rating >7 kV (HBM), >700V (EIAJ)
·Supports VGA, SVGA, XGA and Single Pixel SXGA.
·PLL requires no external components
·Compatible with TIA/EIA-644 LVDS standard
·Low profile 56-lead or 48-lead TSSOP package
·DS90CF386 also available in a 64 ball, 0.8mm fine pitch
·ball grid array (FBGA) package




Pinout

Connection Diagram




Specifications

Function Receiver
Color Depth 24 bpp
Pixel Clock Max 85 MHz
Pixel Clock Min 20 MHz
Output Compatibility LVCMOS
Total Throughput 2380 Mbps
Payload/Channel 595 Mbps
Supply Voltage 3.3 Volt
Temperature Min -10 deg C
Temperature Max 70 deg C
DisplayType FPD
Sensing & Imaging Yes
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Description

The DS90CF386 receiver converts the four LVDS data streams (Up to 2.38 Gbps throughput or 297.5 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF366 that converts the three LVDS data streams (Up to 1.78 Gbps throughput or 223 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling edge strobe transmitter (DS90C385/DS90C365) will interoperate with a Falling edge strobe Receiver without any translation logic.

The DS90CF386 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the 56L TSSOP package.

This chipset DS90CF386 is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Reliability Metrics

Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
DS90CF386MTD CMOS7 0 16561 0 0 954000 4 270700104
DS90CF386MTDX CMOS7 0 16561 0 0 954000 4 270700104
DS90CF386SLC CMOS7 0 16561 0 0 954000 4 270700104
DS90CF386SLCX CMOS7 0 16561 0 0 954000 4 270700104

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


Design Tools

Title Size in Kbytes Date
Evaluation Kit for FPD-Link 20-85MHz 3.3V, 24 bit View

If you have trouble printing or viewing PDF file(s), see Printing Problems.

More Application Notes

Title Size in Kbytes Date
AN-1127: Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link 25 Kbytes 4-Oct-04 Download
AN-1163: Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 13 Kbytes 15-May-04 Download
AN-1085: Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines 304 Kbytes 4-Oct-04 Download
AN-1085 (Japanese): Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines
640){this.height=this.height*640/this.width;this.width=640;}' border="0" alt=" Connection Diagram">		 192 Kbytes

If you have trouble printing or viewing PDF file(s), see Printing Problems.






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