DS90CF363A

Features:

`20 to 65 MHz shift clock support
`Rejects > ± 3ns Jitter from VGA chip with less 225ps output Jitter @65MHz (TJCC)
`BestinClass Set & Hold Times on TxINPUTs
`Tx power consumption <130 mW (typ) @65MHz Grayscale
`>50% Less Power Dissipation than BiCMOS Alternatives
`Tx Power-down mode <200µW (max)
`ESD rating >7 kV (HBM), >500V (EIAJ)
`Supports VGA, SVGA, XGA and Dual Pixel SXGA.
`Narrow bus reduces cable size and cost
`Up to 1.3 Gbps throughput
`Up to 170 Megabytes/sec bandwidth
`345 mV (typ) swing LVDS devices for low EMI
`PLL requires no external components
`Compatible with TIA/EIA-644 LVDS standard
`Low profile 48-lead TSSOP package
`Improved replacement for: SN75LVDS85 - DS90C363A SN75LVDS84 - DS90CF363A


Pinout




Specifications

Supply Voltage (V_CC)                                                                                −0.3V to +4V
CMOS/TTL Input Voltage                                                              −0.3V to (V_CC + 0.3V)
LVDS Driver Output Voltage                                                         −0.3V to (V_CC + 0.3V)
LVDS Output Short Circuit Duration Continuous
Junction Temperature                                                                                       +150°C
Storage Temperature                                                                       −65°C to +150°C
Lead Temperature (Soldering, 4 sec)                                                                +260°C
Maximum Package Power Dissipation Capacity @                                                 25°C
MTD48 (TSSOP) Package: DS90C363A/DS90CF363A                                           1.98 W
Package Derating: DS90C363A/DS90CF363A                        16 mW/°C above +25°C


Description

The DS90C363A/DS90CF363A transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel.

Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90C363A transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin.

The DS90CF363A is fixed as a Falling edge strobe transmitter. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF364) without any translation logic.

This chipset DS90C363A/DS90CF363A is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.