DS90C385A

Features:

Single +3.3V supply
Chipset (Tx + Rx) power consumption <250 mW (typ)
Power-down mode (<0.5 mW total)
Up to 173 Megabytes/sec bandwidth
Up to 1.386 Gbps data throughput
Narrow bus reduces cable size
290 mV swing LVDS devices for low EMI
+1V common mode range (around +1.2V)
PLL requires no external components
Low profile 48-lead TSSOP package
Rising edge data strobe
Compatible with TIA/EIA-644 LVDS standard
ESD Rating > 7kV
Operating Temperature: −40˚C to +85˚C


Specifications

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)                                                               −0.3V to +4V
CMOS/TTL Input Voltage                                             −0.3V to (VCC + 0.3V)
CMOS/TTL Output Voltage                                           −0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage                                       −0.3V to (VCC + 0.3V)
LVDS Driver Output Voltage                                         −0.3V to (VCC + 0.3V)
LVDS Output Short
Circuit Duration Continuous
Junction Temperature                                                                        +150˚C
Storage Temperature Range                                               −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.)                                                                              +260˚C
Maximum Package Power Dissipation @                                               +25˚C
MTD48 (TSSOP) Package:


Description

The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel.

Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s).

The multiplexing of the data lines DS90CR215 provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With
the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.