DS90C383

Features:

20 to 65 MHz shift clock support
Programmable transmitter (DS90C383) strobe select (Rising or Falling edge strobe)
Single 3.3V supply
Chipset (Tx + Rx) power consumption < 250 mW (typ)
Power-down mode (< 0.5 mW total)
Single pixel per clock XGA (1024x768) ready
Supports VGA, SVGA, XGA and higher addressability.
Up to 227 Megabytes/sec bandwidth
Up to 1.8 Gbps throughput
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
PLL requires no external components
Low profile 56-lead TSSOP package.
Also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
Falling edge data strobe Receiver
Compatible with TIA/EIA-644 LVDS standard
ESD rating >7kV
Operating Temperature: −40˚C to +85˚C


Specifications

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (V_CC)                                       −0.3V to +4V
C_MOS/T_TL Input Voltage                     −0.3V to (V_CC + 0.3V)
C_MOS/T_TL Output Voltage                   −0.3V to (V_CC + 0.3V)
L_VDS Receiver Input Voltage               −0.3V to (V_CC + 0.3V)
L_VDS Driver Output Voltage                 −0.3V to (V_CC + 0.3V)
L_VDS Output Short Circuit
Duration Continuous
Junction Temperature                                                 +150˚C
Storage Temperature                                   −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec for T_SSOP)                                       +260˚C
Solder Reflow Temperature
(20 sec for F_BGA)                                                        +220˚C
Maximum Package Power Dissipation Capacity               25˚C
MTD56 (T_SSOP) Package:
DS90C383MTD                                                             1.63 W
DS90CF384MTD                                                           1.61 W
Package Derating:
DS90C383MTD 12.5 mW/˚C above                                +25˚C 


Description

The DS90C383 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of LVCMOS/ LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. Both devices are also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package.

This chipset DS90C383 is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.