DS90C124 Selling Leads, Price trend, DS90C124 DataSheet download, circuit diagram from SeekIC.com

PinoutSpecificationsFunctionDeserializerColor Depth18 bppPixel Clock Max35 MHzPixel Clock Min5 MHzInput CompatibilityFPD- Link II LVDSOutput CompatibilityLVCMOSAEC Q-100 Automotive Grade2EMI ReductionProgressive Turn On (PTO), Slew Rate ControlTotal Throughput840 MbpsPayload/Channel840 MbpsReferen...

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SeekIC No. : 004329313 Detail

DS90C124: PinoutSpecificationsFunctionDeserializerColor Depth18 bppPixel Clock Max35 MHzPixel Clock Min5 MHzInput CompatibilityFPD- Link II LVDSOutput CompatibilityLVCMOSAEC Q-100 Automotive Grade2EMI Reducti...

DS90C124 Data Sheet

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Part Number:: DS90C124
Supply Ability:: 5000

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Qty
1~5000

Unit Price
Negotiable

Processing time
15 Days

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Upload time: 2024/10/20

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Product Details

Description

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Specifications

Function	Deserializer
Color Depth	18 bpp
Pixel Clock Max	35 MHz
Pixel Clock Min	5 MHz
Input Compatibility	FPD- Link II LVDS
Output Compatibility	LVCMOS
AEC Q-100 Automotive Grade	2
EMI Reduction	Progressive Turn On (PTO), Slew Rate Control
Total Throughput	840 Mbps
Payload/Channel	840 Mbps
Reference Clock Req'd Deserializer	No
Embedded Clock	Yes
Special Features	Progressive Turn On (PTO) on Parallel Bus, Slew Rate Control
Eval Kit	SERDES24-35USB
ESD	8 kV
Supply Voltage	3.3 Volt
Temperature Min	-40 deg C
Temperature Max	105 deg C
Automotive Selection Guide	Yes
DisplayType	LCD
PowerWise	No
Communications	No
Sensing & Imaging	Yes
Parallel Bus Width	24 bits
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Description

The DS90C241/DS90C124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90C241/DS90C124 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90C124IVS	CMOS7	0	16561	0	0	954000	4	270700104
DS90C124IVSX	CMOS7	0	16561	0	0	954000	4	270700104
DS90C124QVS	CMOS7	0	16561	0	0	954000	4	270700104
DS90C124QVSX	CMOS7	0	16561	0	0	954000	4	270700104

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Design Tools

Title	Size in Kbytes	Date
LVDS Owner's Manual - 3rd Edition	2 Kbytes	4-Jan-2008	View
Evaluation Kit for DS90C241/DS90C124 Serializer and Deserializer Chipset			View

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Application Notes

Title	Size in Kbytes	Date
AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

DS90C124

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