PinoutSpecificationsFunctionSerializerTotal Throughput3125 MbpsPayload/Channel3125 MbpsSignal ConditioningDe-EmphasisClock Min125 MHzClock Max312.5 MHzInput CompatibilityLVDSOutput CompatibilityCMLReference Clock Req'd DeserializerNoPower Consumption_500 mWReach20 meters CAT6Other Supply2.5SupplyV...
DS32EL0421: PinoutSpecificationsFunctionSerializerTotal Throughput3125 MbpsPayload/Channel3125 MbpsSignal ConditioningDe-EmphasisClock Min125 MHzClock Max312.5 MHzInput CompatibilityLVDSOutput CompatibilityCMLR...
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Function | Serializer |
Total Throughput | 3125 Mbps |
Payload/Channel | 3125 Mbps |
Signal Conditioning | De-Emphasis |
Clock Min | 125 MHz |
Clock Max | 312.5 MHz |
Input Compatibility | LVDS |
Output Compatibility | CML |
Reference Clock Req'd Deserializer | No |
Power Consumption_ | 500 mW |
Reach | 20 meters CAT6 |
Other Supply | 2.5 |
SupplyVoltage | 3.3 Volt |
ESD | 8 kV |
Temperature Min | -40 deg C |
Temperature Max | 85 deg C |
Compression Ratio | 5:1 DDR |
Number Transmitters | 1 |
Communications | Yes |
Sensing & Imaging | Yes |
Parallel Bus Width | 5 bits |
View Using Catalog |
The
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.
Design Tools
Title | Size in Kbytes | Date | |||
High-Performance SerDes Module with Easy FPGA Interface and Cable Detect | View |
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