DS3131

Supply Voltage - Min :
Packaging :
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
Supply Voltage - Max : 3.63 V
Type : Unchannelized Bit-Synchronous HDLC
Package / Case : BGA-272
Data Rate : 132 Mbps
Supply Current : 200 mA


Specifications

Voltage on Any Lead with Respect to V_SS (except V_DD)        -0.3V to 5.5V
Supply Voltage (V_DD) with Respect to V_SS                          -0.3V to 3.63V
Operating Temperature                                                         0 to +70
Storage Temperature                                                       -55to +125
Soldering Temperature                                             260 for 10 seconds                                    


Description

The Layer One Block handles the physical input and output of serial data to and from the DS3131. The DS3131 is capable of operating in a number of modes and can be used in many applications requiring high density and high speed HDLC termination. Section 14 details a few common applications for the DS3131. The Layer One Block prepares the incoming data for the HDLC Block and grooms data from the HDLC Block for transmission. The Layer One Block interfaces directly to the Bit Error Rate Tester (BERT) Block. The BERT Block can generate and detect both pseudorandom and repeating bit patterns and it is used to test and stress data communication links. The BERT Block is a global chip resource that can be assigned to any one of the 40 Bit Synchronous ports.

There are 40 Bit Synchronous HDLC Controllers (one for each port), each of which is capable of operating at speeds up to 52Mbps. The Bit Synchronous HDLC Controllers have serial interfaces. The DS3131 HDLC controllers perform all of the Layer 2 processing which include, zero stuffing and destuffing, flag generation and detection, CRC generation and checking, abort generation and checking.

In the receive path, the following process occurs. The HDLC controllers collect the incoming data and then signal the FIFO that the controller has data to transfer to the FIFO. The 40 ports are priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC controllers to the FIFO Block. The priority of transfer between the HDLC controllers and the FIFO is of no real concern however since the  DS3131 has been designed to handle up to 132Mbps in both the receive and transmit directions without any potential loss of data due to priority conflicts.

The FIFO transfers data from the HDLC Engines into the FIFO and checks to see if the FIFO has filled to beyond the programmable High Water Mark. If it has, then the FIFO signals to the DMA that data is ready to be burst read from the FIFO to the PCI Bus. The FIFO Block controls the DMA Block and it tells the DMA when to transfer data from the FIFO to the PCI Bus. Since the DS3131 can handle multiple HDLC channels, it is quite possible that at any one time, several HDLC channels may need to have data  transferred from the FIFO to the PCI Bus. The FIFO determines which HDLC channel the DMA will handle next via a Host configurable algorithm which allows the selection to be either round robin or priority decoded (with HDLC Channel 1 getting the highest priority). Depending on the application, the selection of this algorithm can be quite important. The DS3131 cannot control when it will be granted PCI Bus access and if bus access is restricted, then the Host may wish to prioritize which HDLC channels get top priority access to the PCI Bus when it is granted to the DS3131.

When the DMA transfers data from the FIFO to the PCI Bus, it burst reads all available data in the FIFO (even if the FIFO contains multiple HDLC packets) and tries to empty the FIFO. If an incoming HDLC packet is not large enough to fill the FIFO to the High Water Mark, then the FIFO will not wait for more data to enter the FIFO, it will signal the DMA that a End Of Frame (EOF) was detected and that data is ready to be transferred from the FIFO to the PCI Bus by the DMA.

In the transmit path, a very similar process occurs. As soon as a HDLC channel is enabled, the HDLC (Layer 2) Engines begin requesting data from the FIFO. Like the receive side, the 40 ports are priority decoded with Port 0 (HDLC Channel #1) getting the highest priority. Hence, if multiple ports are requesting packet data, the FIFO will first satisfy the requirements on all the enabled HDLC channels in the lower numbered ports before moving on to the higher numbered ports. Again there is no potential loss of data as long as the transmit throughput maximum of 132Mbps is not exceeded. When the FIFO detects that a HDLC Engine needs data, it then transfers the data from the FIFO to the HDLC Engines. If the FIFO detects that the FIFO is below the Low Water Mark, it then checks with the DMA to see if there is any data available for that HDLC Channel. The DMA will know if any data is available because the Host on the PCI Bus will have informed it of such via the Pending Queue Descriptor. When the DMA detects that data is available, it informs the FIFO and then the FIFO decides which HDLC channel gets the highest priority to the DMA to transfer data from the PCI Bus into the FIFO. Again, since the DS3131 can handle multiple HDLC channels, it is quite possible that at any one time, several HDLC channels may need the DMA to burst data from the PCI Bus into the FIFO. The FIFO determines which HDLC channel the DMA will handle next via a Host configurable algorithm which allows the selection to be either round robin or priority decoded (with HDLC Channel 1 getting the highest priority).

When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with HDLC packet data even if it that means writing multiple packets. Once the FIFO detects that the DMA has filled it  to beyond the Low Water Mark (or an EOF is reached), the FIFO will begin transferring data to the HDLC controller.

One of the unique attributes of the DS3131 is the structure of the DMA. The DMA has been optimized to maintain maximum flexibility yet reduce the number of bus cycles required to transfer packet data. The DMA uses a flexible scatter/gather technique which allows that packet data to be place anywhere within the 32-bit address space. The user has the option on the receive side of two different buffer sizes which are called "large" and "small" but that can be set to any size up to 8191 bytes. The user has the option to store the incoming data either, only in the large buffers, only in the small buffers, or fill a small buffer first and then fill large buffers as needed. The varying buffer storage options allow the user to make the best use of the available memory and to be able to balance the tradeoff between latency and bus utilization.

The DMA uses a set of descriptors to know where to store the incoming HDLC packet data and where to obtain HDLC packet data that is ready to be transmitted. The descriptors are fixed size messages that are handed back and forth from the DMA to the Host. Since this descriptor transfer utilizes bus cycles, the DMA has been structured to minimize the number of transfers required. For example on the receive side, the DMA obtains descriptors from the Host to know where in the 32-bit address space to place the incoming packet data. These descriptors are known as Free Queue Descriptors. When the DMA reads these descriptors off of the PCI Bus, they contain all the information that the DMA needs to know where to store the incoming data. Unlike other existing scatter/gather DMA architectures, the DS3131 DMA does not need to use any more bus cycles to determine where to place the data. Other DMA architectures tend to use pointers which require them to go back onto the bus to obtain more information and hence use more bus cycles.

Another technique that the DMA uses to maximize bus utilization is the ability to burst read and write the descriptors. The device can be enabled to read and write the descriptors in bursts of 8 or 16 instead of one at a time. Since there is fixed overhead associated with each bus transaction, the ability to burst read and write descriptors allows the device to share the bus overhead among 8 or 16 descriptor transactions which reduces the total number of bus cycles needed.

The DMA can also burst up to 256 dwords (1024 bytes) onto the PCI Bus. This helps to minimize bus cycles by allowing the device to burst large amounts of data in a smaller number of bus transactions which reduces bus cycles by reducing the amount of fixed overhead that is placed on the bus.

When the Local Bus is enabled, ports 28 to 39 (HDLC Channels 29 to 40) are disabled to make room for the signals needed by the Local Bus. The Local Bus Block has two modes of operation. It can used as either a Bridge from the PCI Bus in which case it is a bus master or it can be used as a Configuration Bus in which case it is a bus slave. The Bridge Mode allows the Host on the PCI Bus to access the local bus. The DS3131 will map data from the PCI Bus to the local bus. In the Configuration Mode, the local bus is used only to control and monitor the DS3131 while the HDLC packet data will still be transferred to the Host via the PCI Bus.

Parameters:

Technical/Catalog Information	DS3131
Vendor	Maxim Integrated Products
Category	Integrated Circuits (ICs)
Controller Type	HDLC Controller
Interface	PCI
Voltage - Supply	3 V ~ 3.6 V
Current - Supply	200mA
Package / Case	272-BGA
Packaging	Tube
Operating Temperature	0°C ~ 70°C
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	DS3131 DS3131