DS21348

Features:

  Complete E1, T1, or J1 line interface unit(LIU)
   Supports both long-haul and short-haultrunks
   Internal software-selectable receive-sidetermination for 75Ω/100Ω/120

   3.3V power supply
   32-bit or 128-bit crystal-less jitter attenuatorrequires only a 2.048MHz master clock forboth E1 and T1 with option to use 1.544MHzfor T1
   Generates the appropriate line build-outs,with and without return loss, for E1 andDSX-1 and CSU line build-outs for T1
   AMI, HDB3, and B8ZS, encoding/decoding
   16.384MHz, 8.192MHz, 4.096MHz, or2.048MHz clock output synthesized torecovered clock
   Programmable monitor mode for receiver
   Loopbacks and PRBS pattern generation/detection with output for received errors
   Generates/detects in-band loop codes, 1 to 16bits including CSU loop codes
   8-bit parallel or serial interface with optionalhardware mode
   Muxed and nonmuxed parallel bus supportsIntel or Motorola
   Detects/generates blue (AIS) alarms
   NRZ/bipolar interface for TX/RX data I/O
   Transmit open-circuit detection
   Receive Carrier Loss (RCL) indication(G.775)
   High-Z State for TTIP and TRING
   50mA (rms) current limiter


Pinout




Specifications

Voltage Range on Any Pin Relative to Ground ....................-1.0V to +6.0V
Operating Temperature Range for DS21348TN ....................-40 to +85
Storage Temperature Range ..........................See J STD-020A specification


Description

The DS21348 is a complete selectable E1 or T1 LIU for short-haul and long-haul applications.Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts automatically
o the incoming signal and can be programmed for 0dB to 12 dB or 0dB to 43dB for E1 applications and0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary G.703 E1waveshapes in 75Ω or 120Ω applications and DSX-1 line build outs or CSU line build outs of 0dB,
-7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less onboard jitter attenuator requires only a2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can beplaced in either the transmit or receive datapaths. An X 2.048MHz output clock synthesized to RCLK isavailable for use as a backplane system clock (where n = 1, 2, 4, or 8). The DS21348 has diagnosticcapabilities such as loopbacks and PRBS patterngeneration/detection. 16-bit loop-up and loop-downcodes can be generated and detected. The device canbe controlled via an 8-bit parallel muxed ornonmuxed port, serial port, or used in hardware mode. The device fully meets all of the latest E1 and T1specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR62411, ITU G.703, G.704, G.706,G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703,JTI.431, JJ-20.1, TBR12,TBR13, and CTR4.