Features: Integrated NV SRAM, real time clock, crystal, powerfail control circuit and lithium energy source Clock registers are accessed identical to the static RAM. These registers are resident in the eight top RAM locations. Century byte register Totally nonvolatile with over 10 years of operati...
DS1743P: Features: Integrated NV SRAM, real time clock, crystal, powerfail control circuit and lithium energy source Clock registers are accessed identical to the static RAM. These registers are resident in ...
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Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature 0°C to 70°C
Storage Temperature -40°C to +85°C
Soldering Temperature See J-STD-020A Specification (See Note 8)
8. Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering techniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.
The DS1743 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8 non-volatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1743 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.