DS1646

The DS1646 is a 128k x 8 nonvolatile static RAM with a full-function real time clock, which are both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any JEDEC standard 128k x 8 SRAM. The device DS1646 can also be easily substituted for ROM, EPROM and EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real time clock information resides in the eight uppermost RAM locations. The RTC registers DS1646 contain year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically.

Features of the DS1646 are:(1)integrates NV SRAM, real-time clock,crystal, power-fail control circuit and lithium energy source; (2)clock registers are accessed identically to the static RAM.these registers are resident in the eight top RAM locations; (3)totally nonvolatile with over 10 years of operation in the absence of power; (4)BCD-coded year, month, date, day, hours,minutes, and seconds with leap year compensation valid up to 210.The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1646 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-oftolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.

The absolute maximum ratings of the DS1646 can be summarized as:(1)voltage range on any pin relative to ground:-0.3V to +6.0V;(2)storage temperature range:-40 to +85;(3)soldering temperature:260;(4)lead temperature:260.While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1646 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy.Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was present at the moment the halt command was issued.