Features: • In-System Programmable PROMs for Configuration of
Xilinx FPGAs
• Low-Power Advanced CMOS NOR FLASH Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Industrial Temperature Range
(40°C to +85°C)
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA Configuration
• Cascadable for Storing Longer or Multiple Bitstreams
• Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
• I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V
• Design Support Using the Xilinx Alliance ISE and
Foundation ISE Series Software Packages
• XCF01S/XCF02S/XCF04S
- 3.3V supply voltage
- Serial FPGA configuration interface (up to 33 MHz)
- Available in small-footprint VO20 and VOG20 packages.
• XCF08P/XCF16P/XCF32P
- 1.8V supply voltage
- Serial or parallel FPGA configuration interface (up to 33 MHz)
- Available in small-footprint VO48, VOG48, FS48,
and FSG48 packages
- Design revision technology enables storing and
accessing multiple design revisions for configuration
- Built-in data decompressor compatible with Xilinx
advanced compression technologySpecifications
| Symbol |
Description |
XCF01S, XCF02S,
XCF04S |
XCF08P, XCF16P,
XCF32P |
Units |
| VCCINT |
Internal supply voltage relative to GND |
0.5 to +4.0 |
0.5 to +2.7 |
V |
| VCCO |
I/O supply voltage relative to GND |
0.5 to +4.0 |
0.5 to +4.0 |
V |
| VCCJ |
JTAG I/O supply voltage relative to GND |
0.5 to +4.0 |
0.5 to +4.0 |
V |
| VIN |
Input voltage with respect to GND |
VCCO < 2.5V |
0.5 to +3.6 |
0.5 to +3.6 |
V |
| VCCO 2.5V |
0.5 to +5.5 |
0.5 to +3.6 |
| VTS |
Voltage applied to High-Z output |
VCCO < 2.5V |
0.5 to +3.6 |
0.5 to +3.6 |
V |
| VCCO 2.5V |
0.5 to +5.5 |
0.5 to +3.6 |
| TSTG |
Storage temperature (ambient) |
65 to +150 |
65 to +150 |
°C |
| TJ |
Junction temperature |
+125 |
+125 |
°C |
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can
undershoot to 2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to
200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
3. For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com.DescriptionXilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Megabit (Mbit) densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable methodfor storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that support Master Serial and Slave Serial FPGA configuration modes (Figure 1). The XCFxxP version includes 32-Mbit, 16-Mbit, and 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 2). A summary of the Platform Flash PROM family members and supported features is shown in Table 1.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. With CF High, a short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are both clocked by an external clock source, or optionally, for the XCFxxP PROM only, the PROM can be used to drive the FPGA's configuration clock.
The XCFxxP version of the Platform Flash PROM also supportsMaster SelectMAP and Slave SelectMAP (or Slave Parallel) FPGA configuration modes. When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave SelectMAP Mode, either an external oscillator generates the configuration clock that drives the PROM and the FPGA, or optionally, the XCFxxP PROM can be used to drive the FPGA's configuration clock. With BUSY Low and CF High, after CE and OE are enabled, data is available on the PROMs DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave Parallel /Slave SelecMAP mode.
The XCFxxP version of the Platform Flash PROM provides additional advanced features. A built-in data decompressor supports utilizing compressed PROM files, and design revisioning allows multiple design revisions to be stored on a single PROM or stored across several PROMs. For design revisioning, external pins or internal control bits are used to select the active design revision.
Multiple Platform Flash PROM devices can be cascaded to support the larger configuration files required when targeting larger FPGA devices or targeting multiple FPGAs daisy chained together. When utilizing the advanced features for the XCFxxP Platform Flash PROM, such as design revisioning, programming files which span cascaded PROM devices can only be created for cascaded chains containing only XCFxxP PROMs. If the advanced XCFxxP features arenot enabled, then the cascaded chain can include both XCFxxP and XCFxxS PROMs.
The Platform Flash PROMs are compatible with all of the existing FPGA device families. A reference list of Xilinx FPGAs and the respective compatible Platform Flash PROMs is given in Table 2. A list of Platform Flash PROMs and their capacities is given in Table 3.
DS123 Data Sheet
