DS1009

Supply Voltage V_CC . . . . . . . . . . . . . . . .. . -0.5 to 1.32V
Supply Voltage V_CCAUX . . . . . . . . . . . . . . . -0.5 to 3.75V
Supply Voltage V_CCJ . . . . . . . . . . . . . . . . . -0.5 to 3.75V
Supply Voltage V_CCPLL⁴ . . . . . . . . . . . . . . .-0.5 to 3.75V
Output Supply Voltage V_CCIO . . . . . . . . . . -0.5 to 3.75V
Input or I/O Tristate Voltage Applied5 . . . .-0.5 to 3.75V
Storage Temperature (Ambient) . . . . . . . . . -65 to 150
Junction Temperature Under Bias (T_j) . . . . . . . . . +125
1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. V_CCPLL only available on csBGA, PQFP and TQFP packages.
5. Overshoot and undershoot of -2V to (V_IHMAX + 2) volts is permitted for a duration of <20ns.

DS1009 combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cell s in an architecture referred to as flexiFLASH.

The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live
Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies.

The DS1009 FPGA fabric was optimized for the new technology from the outset with high performance and low cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks.

The ispLEVER^®design tool from Lattice allows large and complex designs to be efficiently implem ented using the LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the v. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification.

Lattice provides many pre-designed Intellectual Property (IP) ispLeverCORE™ modules for the DS1009 family.

By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,increasing their productivity.