Specifications Symbol Description Min Max Units VCCint1 1.8V supply voltage relative toGND -0.5 2.0 V VCCint2 3.3V supply voltage relative toGND -0.5 4.0 V FLASH_VCCO Flash interface power supply -0.5 4.0 V CFG_VCCO Configuration interface powersupply -0.5 4.0 ...
DS087: Specifications Symbol Description Min Max Units VCCint1 1.8V supply voltage relative toGND -0.5 2.0 V VCCint2 3.3V supply voltage relative toGND -0.5 4.0 V FLASH_VCCO Flas...
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Symbol | Description | Min | Max | Units |
VCCint1 | 1.8V supply voltage relative to GND |
-0.5 | 2.0 | V |
VCCint2 | 3.3V supply voltage relative to GND |
-0.5 | 4.0 | V |
FLASH_VCCO | Flash interface power supply | -0.5 | 4.0 | V |
CFG_VCCO | Configuration interface power supply |
-0.5 | 4.0 | V |
CTRL_VCCO | System interface power supply | -0.5 | 4.0 | V |
VIN | Input voltage with respect to GND |
-0.5 | 4.0 | V |
VTS | Voltage applied to 3-state output. | -0.5 | 4.0 | V |
VCCint1_r | Longest 1.8V supply voltage rise time 0 V 1.71 V |
-50 | ms | |
TSTG | Storage temperature (ambient) | -40 | 125 |
The DS087 ACE Multi-Package Module (MPM) solution addresses the need for a space-efficient, pre-engineered, high-density configuration solution in multiple FPGA systems.
The DS087 ACE technology is a ground-breaking in-system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high capacity FPGA systems. As shown in Figure 1, the System ACE MPM solution is a multi-package module that includes DS087 ACE MPM controller, a configuration PROM, and an AMD Flash Memory.
The DS087 ACE MPM has four major interfaces. (See Figure 2.) The boundary scan JTAG interface is provided for boundary scan test and boundary-scan-based Flash memory programming. The system control interface provides an input for the system clock, design set selection pins, system configuration control signals, and system configuration status signals.
The native Flash memory interface provides direct read and write access to the Flash memory unit. The target FPGA interface provides the signals to configure target FPGAs via the Slave-Serial, concurrent Slave-Serial, or SelectMAP configuration modes.
Separate power pins provide voltage compatibility control for the target FPGA configuration interface and for the system control/status interface.
See Figure 3 for a complete view of the components and schematic of the signals in the DS087